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![Rikard Falkeborn](/assets/img/avatar_default.png)
These are only put in an array of pointers to const attribute_group structs. Make them const like the other static attribute_group structs to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20210605221514.73449-1-rikard.falkeborn@gmail.com Signed-off-by: Will Deacon <will@kernel.org>
497 lines
13 KiB
C
497 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* HiSilicon PA uncore Hardware event counters support
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*
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* Copyright (C) 2020 HiSilicon Limited
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* Author: Shaokun Zhang <zhangshaokun@hisilicon.com>
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*
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* This code is based on the uncore PMUs like arm-cci and arm-ccn.
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*/
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#include <linux/acpi.h>
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#include <linux/cpuhotplug.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/list.h>
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#include <linux/smp.h>
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#include "hisi_uncore_pmu.h"
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/* PA register definition */
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#define PA_PERF_CTRL 0x1c00
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#define PA_EVENT_CTRL 0x1c04
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#define PA_TT_CTRL 0x1c08
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#define PA_TGTID_CTRL 0x1c14
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#define PA_SRCID_CTRL 0x1c18
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#define PA_INT_MASK 0x1c70
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#define PA_INT_STATUS 0x1c78
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#define PA_INT_CLEAR 0x1c7c
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#define PA_EVENT_TYPE0 0x1c80
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#define PA_PMU_VERSION 0x1cf0
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#define PA_EVENT_CNT0_L 0x1f00
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#define PA_EVTYPE_MASK 0xff
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#define PA_NR_COUNTERS 0x8
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#define PA_PERF_CTRL_EN BIT(0)
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#define PA_TRACETAG_EN BIT(4)
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#define PA_TGTID_EN BIT(11)
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#define PA_SRCID_EN BIT(11)
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#define PA_TGTID_NONE 0
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#define PA_SRCID_NONE 0
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#define PA_TGTID_MSK_SHIFT 12
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#define PA_SRCID_MSK_SHIFT 12
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HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_cmd, config1, 10, 0);
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HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_msk, config1, 21, 11);
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HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 32, 22);
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HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 43, 33);
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HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 44, 44);
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static void hisi_pa_pmu_enable_tracetag(struct perf_event *event)
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{
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struct hisi_pmu *pa_pmu = to_hisi_pmu(event->pmu);
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u32 tt_en = hisi_get_tracetag_en(event);
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if (tt_en) {
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u32 val;
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val = readl(pa_pmu->base + PA_TT_CTRL);
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val |= PA_TRACETAG_EN;
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writel(val, pa_pmu->base + PA_TT_CTRL);
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}
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}
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static void hisi_pa_pmu_clear_tracetag(struct perf_event *event)
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{
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struct hisi_pmu *pa_pmu = to_hisi_pmu(event->pmu);
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u32 tt_en = hisi_get_tracetag_en(event);
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if (tt_en) {
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u32 val;
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val = readl(pa_pmu->base + PA_TT_CTRL);
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val &= ~PA_TRACETAG_EN;
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writel(val, pa_pmu->base + PA_TT_CTRL);
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}
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}
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static void hisi_pa_pmu_config_tgtid(struct perf_event *event)
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{
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struct hisi_pmu *pa_pmu = to_hisi_pmu(event->pmu);
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u32 cmd = hisi_get_tgtid_cmd(event);
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if (cmd) {
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u32 msk = hisi_get_tgtid_msk(event);
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u32 val = cmd | PA_TGTID_EN | (msk << PA_TGTID_MSK_SHIFT);
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writel(val, pa_pmu->base + PA_TGTID_CTRL);
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}
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}
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static void hisi_pa_pmu_clear_tgtid(struct perf_event *event)
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{
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struct hisi_pmu *pa_pmu = to_hisi_pmu(event->pmu);
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u32 cmd = hisi_get_tgtid_cmd(event);
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if (cmd)
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writel(PA_TGTID_NONE, pa_pmu->base + PA_TGTID_CTRL);
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}
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static void hisi_pa_pmu_config_srcid(struct perf_event *event)
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{
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struct hisi_pmu *pa_pmu = to_hisi_pmu(event->pmu);
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u32 cmd = hisi_get_srcid_cmd(event);
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if (cmd) {
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u32 msk = hisi_get_srcid_msk(event);
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u32 val = cmd | PA_SRCID_EN | (msk << PA_SRCID_MSK_SHIFT);
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writel(val, pa_pmu->base + PA_SRCID_CTRL);
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}
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}
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static void hisi_pa_pmu_clear_srcid(struct perf_event *event)
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{
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struct hisi_pmu *pa_pmu = to_hisi_pmu(event->pmu);
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u32 cmd = hisi_get_srcid_cmd(event);
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if (cmd)
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writel(PA_SRCID_NONE, pa_pmu->base + PA_SRCID_CTRL);
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}
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static void hisi_pa_pmu_enable_filter(struct perf_event *event)
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{
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if (event->attr.config1 != 0x0) {
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hisi_pa_pmu_enable_tracetag(event);
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hisi_pa_pmu_config_srcid(event);
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hisi_pa_pmu_config_tgtid(event);
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}
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}
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static void hisi_pa_pmu_disable_filter(struct perf_event *event)
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{
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if (event->attr.config1 != 0x0) {
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hisi_pa_pmu_clear_tgtid(event);
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hisi_pa_pmu_clear_srcid(event);
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hisi_pa_pmu_clear_tracetag(event);
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}
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}
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static u32 hisi_pa_pmu_get_counter_offset(int idx)
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{
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return (PA_EVENT_CNT0_L + idx * 8);
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}
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static u64 hisi_pa_pmu_read_counter(struct hisi_pmu *pa_pmu,
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struct hw_perf_event *hwc)
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{
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return readq(pa_pmu->base + hisi_pa_pmu_get_counter_offset(hwc->idx));
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}
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static void hisi_pa_pmu_write_counter(struct hisi_pmu *pa_pmu,
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struct hw_perf_event *hwc, u64 val)
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{
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writeq(val, pa_pmu->base + hisi_pa_pmu_get_counter_offset(hwc->idx));
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}
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static void hisi_pa_pmu_write_evtype(struct hisi_pmu *pa_pmu, int idx,
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u32 type)
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{
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u32 reg, reg_idx, shift, val;
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/*
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* Select the appropriate event select register(PA_EVENT_TYPE0/1).
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* There are 2 event select registers for the 8 hardware counters.
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* Event code is 8-bits and for the former 4 hardware counters,
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* PA_EVENT_TYPE0 is chosen. For the latter 4 hardware counters,
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* PA_EVENT_TYPE1 is chosen.
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*/
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reg = PA_EVENT_TYPE0 + (idx / 4) * 4;
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reg_idx = idx % 4;
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shift = 8 * reg_idx;
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/* Write event code to pa_EVENT_TYPEx Register */
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val = readl(pa_pmu->base + reg);
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val &= ~(PA_EVTYPE_MASK << shift);
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val |= (type << shift);
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writel(val, pa_pmu->base + reg);
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}
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static void hisi_pa_pmu_start_counters(struct hisi_pmu *pa_pmu)
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{
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u32 val;
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val = readl(pa_pmu->base + PA_PERF_CTRL);
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val |= PA_PERF_CTRL_EN;
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writel(val, pa_pmu->base + PA_PERF_CTRL);
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}
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static void hisi_pa_pmu_stop_counters(struct hisi_pmu *pa_pmu)
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{
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u32 val;
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val = readl(pa_pmu->base + PA_PERF_CTRL);
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val &= ~(PA_PERF_CTRL_EN);
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writel(val, pa_pmu->base + PA_PERF_CTRL);
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}
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static void hisi_pa_pmu_enable_counter(struct hisi_pmu *pa_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Enable counter index in PA_EVENT_CTRL register */
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val = readl(pa_pmu->base + PA_EVENT_CTRL);
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val |= 1 << hwc->idx;
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writel(val, pa_pmu->base + PA_EVENT_CTRL);
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}
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static void hisi_pa_pmu_disable_counter(struct hisi_pmu *pa_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Clear counter index in PA_EVENT_CTRL register */
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val = readl(pa_pmu->base + PA_EVENT_CTRL);
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val &= ~(1 << hwc->idx);
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writel(val, pa_pmu->base + PA_EVENT_CTRL);
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}
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static void hisi_pa_pmu_enable_counter_int(struct hisi_pmu *pa_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Write 0 to enable interrupt */
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val = readl(pa_pmu->base + PA_INT_MASK);
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val &= ~(1 << hwc->idx);
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writel(val, pa_pmu->base + PA_INT_MASK);
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}
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static void hisi_pa_pmu_disable_counter_int(struct hisi_pmu *pa_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Write 1 to mask interrupt */
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val = readl(pa_pmu->base + PA_INT_MASK);
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val |= 1 << hwc->idx;
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writel(val, pa_pmu->base + PA_INT_MASK);
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}
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static u32 hisi_pa_pmu_get_int_status(struct hisi_pmu *pa_pmu)
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{
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return readl(pa_pmu->base + PA_INT_STATUS);
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}
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static void hisi_pa_pmu_clear_int_status(struct hisi_pmu *pa_pmu, int idx)
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{
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writel(1 << idx, pa_pmu->base + PA_INT_CLEAR);
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}
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static const struct acpi_device_id hisi_pa_pmu_acpi_match[] = {
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{ "HISI0273", },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, hisi_pa_pmu_acpi_match);
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static int hisi_pa_pmu_init_data(struct platform_device *pdev,
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struct hisi_pmu *pa_pmu)
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{
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/*
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* Use the SCCL_ID and the index ID to identify the PA PMU,
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* while SCCL_ID is the nearst SCCL_ID from this SICL and
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* CPU core is chosen from this SCCL to manage this PMU.
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*/
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if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
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&pa_pmu->sccl_id)) {
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dev_err(&pdev->dev, "Cannot read sccl-id!\n");
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return -EINVAL;
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}
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if (device_property_read_u32(&pdev->dev, "hisilicon,idx-id",
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&pa_pmu->index_id)) {
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dev_err(&pdev->dev, "Cannot read idx-id!\n");
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return -EINVAL;
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}
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pa_pmu->ccl_id = -1;
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pa_pmu->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pa_pmu->base)) {
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dev_err(&pdev->dev, "ioremap failed for pa_pmu resource.\n");
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return PTR_ERR(pa_pmu->base);
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}
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pa_pmu->identifier = readl(pa_pmu->base + PA_PMU_VERSION);
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return 0;
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}
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static struct attribute *hisi_pa_pmu_v2_format_attr[] = {
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HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
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HISI_PMU_FORMAT_ATTR(tgtid_cmd, "config1:0-10"),
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HISI_PMU_FORMAT_ATTR(tgtid_msk, "config1:11-21"),
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HISI_PMU_FORMAT_ATTR(srcid_cmd, "config1:22-32"),
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HISI_PMU_FORMAT_ATTR(srcid_msk, "config1:33-43"),
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HISI_PMU_FORMAT_ATTR(tracetag_en, "config1:44"),
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NULL,
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};
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static const struct attribute_group hisi_pa_pmu_v2_format_group = {
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.name = "format",
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.attrs = hisi_pa_pmu_v2_format_attr,
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};
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static struct attribute *hisi_pa_pmu_v2_events_attr[] = {
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HISI_PMU_EVENT_ATTR(rx_req, 0x40),
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HISI_PMU_EVENT_ATTR(tx_req, 0x5c),
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HISI_PMU_EVENT_ATTR(cycle, 0x78),
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NULL
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};
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static const struct attribute_group hisi_pa_pmu_v2_events_group = {
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.name = "events",
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.attrs = hisi_pa_pmu_v2_events_attr,
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};
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static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
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static struct attribute *hisi_pa_pmu_cpumask_attrs[] = {
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&dev_attr_cpumask.attr,
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NULL
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};
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static const struct attribute_group hisi_pa_pmu_cpumask_attr_group = {
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.attrs = hisi_pa_pmu_cpumask_attrs,
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};
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static struct device_attribute hisi_pa_pmu_identifier_attr =
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__ATTR(identifier, 0444, hisi_uncore_pmu_identifier_attr_show, NULL);
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static struct attribute *hisi_pa_pmu_identifier_attrs[] = {
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&hisi_pa_pmu_identifier_attr.attr,
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NULL
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};
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static const struct attribute_group hisi_pa_pmu_identifier_group = {
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.attrs = hisi_pa_pmu_identifier_attrs,
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};
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static const struct attribute_group *hisi_pa_pmu_v2_attr_groups[] = {
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&hisi_pa_pmu_v2_format_group,
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&hisi_pa_pmu_v2_events_group,
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&hisi_pa_pmu_cpumask_attr_group,
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&hisi_pa_pmu_identifier_group,
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NULL
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};
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static const struct hisi_uncore_ops hisi_uncore_pa_ops = {
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.write_evtype = hisi_pa_pmu_write_evtype,
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.get_event_idx = hisi_uncore_pmu_get_event_idx,
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.start_counters = hisi_pa_pmu_start_counters,
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.stop_counters = hisi_pa_pmu_stop_counters,
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.enable_counter = hisi_pa_pmu_enable_counter,
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.disable_counter = hisi_pa_pmu_disable_counter,
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.enable_counter_int = hisi_pa_pmu_enable_counter_int,
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.disable_counter_int = hisi_pa_pmu_disable_counter_int,
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.write_counter = hisi_pa_pmu_write_counter,
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.read_counter = hisi_pa_pmu_read_counter,
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.get_int_status = hisi_pa_pmu_get_int_status,
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.clear_int_status = hisi_pa_pmu_clear_int_status,
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.enable_filter = hisi_pa_pmu_enable_filter,
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.disable_filter = hisi_pa_pmu_disable_filter,
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};
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static int hisi_pa_pmu_dev_probe(struct platform_device *pdev,
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struct hisi_pmu *pa_pmu)
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{
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int ret;
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ret = hisi_pa_pmu_init_data(pdev, pa_pmu);
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if (ret)
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return ret;
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ret = hisi_uncore_pmu_init_irq(pa_pmu, pdev);
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if (ret)
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return ret;
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pa_pmu->pmu_events.attr_groups = hisi_pa_pmu_v2_attr_groups;
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pa_pmu->num_counters = PA_NR_COUNTERS;
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pa_pmu->ops = &hisi_uncore_pa_ops;
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pa_pmu->check_event = 0xB0;
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pa_pmu->counter_bits = 64;
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pa_pmu->dev = &pdev->dev;
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pa_pmu->on_cpu = -1;
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return 0;
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}
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static int hisi_pa_pmu_probe(struct platform_device *pdev)
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{
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struct hisi_pmu *pa_pmu;
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char *name;
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int ret;
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pa_pmu = devm_kzalloc(&pdev->dev, sizeof(*pa_pmu), GFP_KERNEL);
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if (!pa_pmu)
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return -ENOMEM;
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ret = hisi_pa_pmu_dev_probe(pdev, pa_pmu);
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if (ret)
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return ret;
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/*
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* PA is attached in SICL and the CPU core is chosen to manage this
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* PMU which is the nearest SCCL, while its SCCL_ID is greater than
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* one with the SICL_ID.
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*/
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name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sicl%u_pa%u",
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pa_pmu->sccl_id - 1, pa_pmu->index_id);
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if (!name)
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return -ENOMEM;
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ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE,
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&pa_pmu->node);
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if (ret) {
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dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
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return ret;
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}
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pa_pmu->pmu = (struct pmu) {
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.module = THIS_MODULE,
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.task_ctx_nr = perf_invalid_context,
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.event_init = hisi_uncore_pmu_event_init,
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.pmu_enable = hisi_uncore_pmu_enable,
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.pmu_disable = hisi_uncore_pmu_disable,
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.add = hisi_uncore_pmu_add,
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.del = hisi_uncore_pmu_del,
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.start = hisi_uncore_pmu_start,
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.stop = hisi_uncore_pmu_stop,
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.read = hisi_uncore_pmu_read,
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.attr_groups = pa_pmu->pmu_events.attr_groups,
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
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};
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ret = perf_pmu_register(&pa_pmu->pmu, name, -1);
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if (ret) {
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dev_err(pa_pmu->dev, "PMU register failed, ret = %d\n", ret);
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cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE,
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&pa_pmu->node);
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return ret;
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}
|
|
|
|
platform_set_drvdata(pdev, pa_pmu);
|
|
return ret;
|
|
}
|
|
|
|
static int hisi_pa_pmu_remove(struct platform_device *pdev)
|
|
{
|
|
struct hisi_pmu *pa_pmu = platform_get_drvdata(pdev);
|
|
|
|
perf_pmu_unregister(&pa_pmu->pmu);
|
|
cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE,
|
|
&pa_pmu->node);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver hisi_pa_pmu_driver = {
|
|
.driver = {
|
|
.name = "hisi_pa_pmu",
|
|
.acpi_match_table = hisi_pa_pmu_acpi_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = hisi_pa_pmu_probe,
|
|
.remove = hisi_pa_pmu_remove,
|
|
};
|
|
|
|
static int __init hisi_pa_pmu_module_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE,
|
|
"AP_PERF_ARM_HISI_PA_ONLINE",
|
|
hisi_uncore_pmu_online_cpu,
|
|
hisi_uncore_pmu_offline_cpu);
|
|
if (ret) {
|
|
pr_err("PA PMU: cpuhp state setup failed, ret = %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = platform_driver_register(&hisi_pa_pmu_driver);
|
|
if (ret)
|
|
cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE);
|
|
|
|
return ret;
|
|
}
|
|
module_init(hisi_pa_pmu_module_init);
|
|
|
|
static void __exit hisi_pa_pmu_module_exit(void)
|
|
{
|
|
platform_driver_unregister(&hisi_pa_pmu_driver);
|
|
cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE);
|
|
}
|
|
module_exit(hisi_pa_pmu_module_exit);
|
|
|
|
MODULE_DESCRIPTION("HiSilicon Protocol Adapter uncore PMU driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
|
|
MODULE_AUTHOR("Qi Liu <liuqi115@huawei.com>");
|