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![Heiko Stuebner](/assets/img/avatar_default.png)
The separation of pinctrl and gpio drivers created a tiny window where
a pinconfig setting might produce a null-pointer dereference.
The affected device were rk3288-veyron devices in this case.
Pinctrl-hogs are claimed when the pinctrl driver is registered,
at which point their pinconfig settings will be applied.
At this time the now separate gpio devices will not have been created
yet and the matching driver won't have probed yet, making the gpio->foo()
call run into a null-ptr.
As probing is not really guaranteed to have been completed at a specific
time, introduce a queue that can hold the output settings until the gpio
driver has probed and will (in a separate patch) fetch the elements
of the list.
We expect the gpio driver to empty the list, but will nevertheless empty
it ourself on remove if that didn't happen.
Fixes: 9ce9a02039
("pinctrl/rockchip: drop the gpio related codes")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210913224926.1260726-4-heiko@sntech.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
297 lines
7.8 KiB
C
297 lines
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
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*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* With some ideas taken from pinctrl-samsung:
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2012 Linaro Ltd
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* https://www.linaro.org
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*
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* and pinctrl-at91:
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* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*/
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#ifndef _PINCTRL_ROCKCHIP_H
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#define _PINCTRL_ROCKCHIP_H
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enum rockchip_pinctrl_type {
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PX30,
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RV1108,
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RK2928,
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RK3066B,
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RK3128,
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RK3188,
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RK3288,
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RK3308,
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RK3368,
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RK3399,
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RK3568,
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};
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/**
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* struct rockchip_gpio_regs
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* @port_dr: data register
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* @port_ddr: data direction register
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* @int_en: interrupt enable
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* @int_mask: interrupt mask
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* @int_type: interrupt trigger type, such as high, low, edge trriger type.
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* @int_polarity: interrupt polarity enable register
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* @int_bothedge: interrupt bothedge enable register
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* @int_status: interrupt status register
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* @int_rawstatus: int_status = int_rawstatus & int_mask
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* @debounce: enable debounce for interrupt signal
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* @dbclk_div_en: enable divider for debounce clock
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* @dbclk_div_con: setting for divider of debounce clock
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* @port_eoi: end of interrupt of the port
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* @ext_port: port data from external
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* @version_id: controller version register
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*/
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struct rockchip_gpio_regs {
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u32 port_dr;
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u32 port_ddr;
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u32 int_en;
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u32 int_mask;
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u32 int_type;
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u32 int_polarity;
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u32 int_bothedge;
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u32 int_status;
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u32 int_rawstatus;
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u32 debounce;
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u32 dbclk_div_en;
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u32 dbclk_div_con;
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u32 port_eoi;
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u32 ext_port;
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u32 version_id;
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};
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/**
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* struct rockchip_iomux
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* @type: iomux variant using IOMUX_* constants
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* @offset: if initialized to -1 it will be autocalculated, by specifying
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* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following iomux registers.
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*/
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struct rockchip_iomux {
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int type;
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int offset;
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};
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/*
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* enum type index corresponding to rockchip_perpin_drv_list arrays index.
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*/
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enum rockchip_pin_drv_type {
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DRV_TYPE_IO_DEFAULT = 0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_3V0_AUTO,
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DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_MAX
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};
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/*
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* enum type index corresponding to rockchip_pull_list arrays index.
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*/
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enum rockchip_pin_pull_type {
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PULL_TYPE_IO_DEFAULT = 0,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_MAX
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};
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/**
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* struct rockchip_drv
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* @drv_type: drive strength variant using rockchip_perpin_drv_type
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* @offset: if initialized to -1 it will be autocalculated, by specifying
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* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following drive strength
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* registers. if used chips own cal_drv func instead to calculate
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* registers offset, the variant could be ignored.
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*/
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struct rockchip_drv {
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enum rockchip_pin_drv_type drv_type;
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int offset;
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};
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/**
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* struct rockchip_pin_bank
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* @dev: the pinctrl device bind to the bank
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* @reg_base: register base of the gpio bank
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* @regmap_pull: optional separate register for additional pull settings
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* @clk: clock of the gpio bank
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* @db_clk: clock of the gpio debounce
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* @irq: interrupt of the gpio bank
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* @saved_masks: Saved content of GPIO_INTEN at suspend time.
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* @pin_base: first pin number
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* @nr_pins: number of pins in this bank
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* @name: name of the bank
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* @bank_num: number of the bank, to account for holes
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* @iomux: array describing the 4 iomux sources of the bank
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* @drv: array describing the 4 drive strength sources of the bank
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* @pull_type: array describing the 4 pull type sources of the bank
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* @valid: is all necessary information present
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* @of_node: dt node of this bank
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* @drvdata: common pinctrl basedata
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* @domain: irqdomain of the gpio bank
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* @gpio_chip: gpiolib chip
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* @grange: gpio range
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* @slock: spinlock for the gpio bank
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* @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
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* @recalced_mask: bit mask to indicate a need to recalulate the mask
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* @route_mask: bits describing the routing pins of per bank
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* @deferred_output: gpio output settings to be done after gpio bank probed
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* @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
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*/
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struct rockchip_pin_bank {
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struct device *dev;
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void __iomem *reg_base;
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struct regmap *regmap_pull;
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struct clk *clk;
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struct clk *db_clk;
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int irq;
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u32 saved_masks;
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u32 pin_base;
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u8 nr_pins;
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char *name;
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u8 bank_num;
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struct rockchip_iomux iomux[4];
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struct rockchip_drv drv[4];
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enum rockchip_pin_pull_type pull_type[4];
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bool valid;
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struct device_node *of_node;
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struct rockchip_pinctrl *drvdata;
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struct irq_domain *domain;
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range grange;
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raw_spinlock_t slock;
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const struct rockchip_gpio_regs *gpio_regs;
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u32 gpio_type;
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u32 toggle_edge_mode;
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u32 recalced_mask;
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u32 route_mask;
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struct list_head deferred_output;
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struct mutex deferred_lock;
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};
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/**
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* struct rockchip_mux_recalced_data: represent a pin iomux data.
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* @num: bank number.
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* @pin: pin number.
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* @bit: index at register.
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* @reg: register offset.
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* @mask: mask bit
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*/
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struct rockchip_mux_recalced_data {
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u8 num;
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u8 pin;
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u32 reg;
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u8 bit;
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u8 mask;
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};
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enum rockchip_mux_route_location {
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ROCKCHIP_ROUTE_SAME = 0,
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ROCKCHIP_ROUTE_PMU,
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ROCKCHIP_ROUTE_GRF,
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};
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/**
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* struct rockchip_mux_recalced_data: represent a pin iomux data.
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* @bank_num: bank number.
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* @pin: index at register or used to calc index.
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* @func: the min pin.
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* @route_location: the mux route location (same, pmu, grf).
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* @route_offset: the max pin.
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* @route_val: the register offset.
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*/
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struct rockchip_mux_route_data {
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u8 bank_num;
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u8 pin;
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u8 func;
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enum rockchip_mux_route_location route_location;
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u32 route_offset;
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u32 route_val;
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};
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struct rockchip_pin_ctrl {
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struct rockchip_pin_bank *pin_banks;
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u32 nr_banks;
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u32 nr_pins;
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char *label;
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enum rockchip_pinctrl_type type;
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int grf_mux_offset;
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int pmu_mux_offset;
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int grf_drv_offset;
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int pmu_drv_offset;
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struct rockchip_mux_recalced_data *iomux_recalced;
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u32 niomux_recalced;
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struct rockchip_mux_route_data *iomux_routes;
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u32 niomux_routes;
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void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit);
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void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit);
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int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit);
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};
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struct rockchip_pin_config {
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unsigned int func;
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unsigned long *configs;
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unsigned int nconfigs;
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};
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struct rockchip_pin_output_deferred {
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struct list_head head;
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unsigned int pin;
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u32 arg;
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};
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/**
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* struct rockchip_pin_group: represent group of pins of a pinmux function.
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* @name: name of the pin group, used to lookup the group.
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* @pins: the pins included in this group.
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* @npins: number of pins included in this group.
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* @data: local pin configuration
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*/
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struct rockchip_pin_group {
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const char *name;
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unsigned int npins;
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unsigned int *pins;
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struct rockchip_pin_config *data;
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};
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/**
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* struct rockchip_pmx_func: represent a pin function.
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* @name: name of the pin function, used to lookup the function.
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* @groups: one or more names of pin groups that provide this function.
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* @ngroups: number of groups included in @groups.
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*/
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struct rockchip_pmx_func {
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const char *name;
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const char **groups;
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u8 ngroups;
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};
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struct rockchip_pinctrl {
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struct regmap *regmap_base;
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int reg_size;
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struct regmap *regmap_pull;
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struct regmap *regmap_pmu;
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struct device *dev;
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struct rockchip_pin_ctrl *ctrl;
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struct pinctrl_desc pctl;
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struct pinctrl_dev *pctl_dev;
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struct rockchip_pin_group *groups;
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unsigned int ngroups;
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struct rockchip_pmx_func *functions;
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unsigned int nfunctions;
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};
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#endif
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