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![Mika Westerberg](/assets/img/avatar_default.png)
When Software CM is running it should not send any NHI mailbox command during PM flows. Only force power bit needs to be set and cleared so change Tiger Lake (well and Ice Lake) nhi_ops to take this into account. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
185 lines
4.3 KiB
C
185 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* NHI specific operations
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*
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* Copyright (C) 2019, Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*/
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#include <linux/delay.h>
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#include <linux/suspend.h>
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#include "nhi.h"
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#include "nhi_regs.h"
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#include "tb.h"
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/* Ice Lake specific NHI operations */
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#define ICL_LC_MAILBOX_TIMEOUT 500 /* ms */
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static int check_for_device(struct device *dev, void *data)
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{
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return tb_is_switch(dev);
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}
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static bool icl_nhi_is_device_connected(struct tb_nhi *nhi)
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{
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struct tb *tb = pci_get_drvdata(nhi->pdev);
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int ret;
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ret = device_for_each_child(&tb->root_switch->dev, NULL,
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check_for_device);
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return ret > 0;
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}
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static int icl_nhi_force_power(struct tb_nhi *nhi, bool power)
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{
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u32 vs_cap;
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/*
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* The Thunderbolt host controller is present always in Ice Lake
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* but the firmware may not be loaded and running (depending
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* whether there is device connected and so on). Each time the
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* controller is used we need to "Force Power" it first and wait
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* for the firmware to indicate it is up and running. This "Force
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* Power" is really not about actually powering on/off the
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* controller so it is accessible even if "Force Power" is off.
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*
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* The actual power management happens inside shared ACPI power
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* resources using standard ACPI methods.
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*/
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pci_read_config_dword(nhi->pdev, VS_CAP_22, &vs_cap);
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if (power) {
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vs_cap &= ~VS_CAP_22_DMA_DELAY_MASK;
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vs_cap |= 0x22 << VS_CAP_22_DMA_DELAY_SHIFT;
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vs_cap |= VS_CAP_22_FORCE_POWER;
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} else {
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vs_cap &= ~VS_CAP_22_FORCE_POWER;
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}
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pci_write_config_dword(nhi->pdev, VS_CAP_22, vs_cap);
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if (power) {
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unsigned int retries = 350;
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u32 val;
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/* Wait until the firmware tells it is up and running */
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do {
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pci_read_config_dword(nhi->pdev, VS_CAP_9, &val);
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if (val & VS_CAP_9_FW_READY)
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return 0;
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usleep_range(3000, 3100);
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} while (--retries);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void icl_nhi_lc_mailbox_cmd(struct tb_nhi *nhi, enum icl_lc_mailbox_cmd cmd)
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{
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u32 data;
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data = (cmd << VS_CAP_19_CMD_SHIFT) & VS_CAP_19_CMD_MASK;
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pci_write_config_dword(nhi->pdev, VS_CAP_19, data | VS_CAP_19_VALID);
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}
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static int icl_nhi_lc_mailbox_cmd_complete(struct tb_nhi *nhi, int timeout)
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{
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unsigned long end;
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u32 data;
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if (!timeout)
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goto clear;
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end = jiffies + msecs_to_jiffies(timeout);
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do {
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pci_read_config_dword(nhi->pdev, VS_CAP_18, &data);
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if (data & VS_CAP_18_DONE)
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goto clear;
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usleep_range(1000, 1100);
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} while (time_before(jiffies, end));
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return -ETIMEDOUT;
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clear:
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/* Clear the valid bit */
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pci_write_config_dword(nhi->pdev, VS_CAP_19, 0);
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return 0;
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}
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static void icl_nhi_set_ltr(struct tb_nhi *nhi)
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{
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u32 max_ltr, ltr;
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pci_read_config_dword(nhi->pdev, VS_CAP_16, &max_ltr);
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max_ltr &= 0xffff;
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/* Program the same value for both snoop and no-snoop */
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ltr = max_ltr << 16 | max_ltr;
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pci_write_config_dword(nhi->pdev, VS_CAP_15, ltr);
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}
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static int icl_nhi_suspend(struct tb_nhi *nhi)
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{
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struct tb *tb = pci_get_drvdata(nhi->pdev);
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int ret;
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if (icl_nhi_is_device_connected(nhi))
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return 0;
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if (tb_switch_is_icm(tb->root_switch)) {
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/*
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* If there is no device connected we need to perform
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* both: a handshake through LC mailbox and force power
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* down before entering D3.
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*/
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icl_nhi_lc_mailbox_cmd(nhi, ICL_LC_PREPARE_FOR_RESET);
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ret = icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
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if (ret)
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return ret;
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}
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return icl_nhi_force_power(nhi, false);
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}
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static int icl_nhi_suspend_noirq(struct tb_nhi *nhi, bool wakeup)
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{
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struct tb *tb = pci_get_drvdata(nhi->pdev);
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enum icl_lc_mailbox_cmd cmd;
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if (!pm_suspend_via_firmware())
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return icl_nhi_suspend(nhi);
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if (!tb_switch_is_icm(tb->root_switch))
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return 0;
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cmd = wakeup ? ICL_LC_GO2SX : ICL_LC_GO2SX_NO_WAKE;
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icl_nhi_lc_mailbox_cmd(nhi, cmd);
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return icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT);
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}
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static int icl_nhi_resume(struct tb_nhi *nhi)
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{
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int ret;
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ret = icl_nhi_force_power(nhi, true);
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if (ret)
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return ret;
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icl_nhi_set_ltr(nhi);
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return 0;
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}
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static void icl_nhi_shutdown(struct tb_nhi *nhi)
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{
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icl_nhi_force_power(nhi, false);
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}
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const struct tb_nhi_ops icl_nhi_ops = {
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.init = icl_nhi_resume,
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.suspend_noirq = icl_nhi_suspend_noirq,
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.resume_noirq = icl_nhi_resume,
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.runtime_suspend = icl_nhi_suspend,
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.runtime_resume = icl_nhi_resume,
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.shutdown = icl_nhi_shutdown,
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};
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