528 lines
12 KiB
C
528 lines
12 KiB
C
// SPDX-License-Identifier: BSD-3-Clause-Clear
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/*
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* Copyright (c) 2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/msi.h>
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#include <linux/pci.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/ioport.h>
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#include "core.h"
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#include "debug.h"
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#include "mhi.h"
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#include "pci.h"
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#include "pcic.h"
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#define MHI_TIMEOUT_DEFAULT_MS 20000
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#define RDDM_DUMP_SIZE 0x420000
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static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = {
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{
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.num = 0,
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.name = "LOOPBACK",
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.num_elements = 32,
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.event_ring = 0,
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.dir = DMA_TO_DEVICE,
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.ee_mask = 0x4,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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},
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{
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.num = 1,
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.name = "LOOPBACK",
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.num_elements = 32,
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.event_ring = 0,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = 0x4,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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},
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{
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.num = 20,
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.name = "IPCR",
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.num_elements = 64,
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.event_ring = 1,
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.dir = DMA_TO_DEVICE,
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.ee_mask = 0x4,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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},
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{
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.num = 21,
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.name = "IPCR",
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.num_elements = 64,
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.event_ring = 1,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = 0x4,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = true,
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},
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};
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static struct mhi_event_config ath11k_mhi_events_qca6390[] = {
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{
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.num_elements = 32,
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.irq_moderation_ms = 0,
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.irq = 1,
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.mode = MHI_DB_BRST_DISABLE,
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.data_type = MHI_ER_CTRL,
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.hardware_event = false,
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.client_managed = false,
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.offload_channel = false,
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},
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{
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.num_elements = 256,
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.irq_moderation_ms = 1,
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.irq = 2,
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.mode = MHI_DB_BRST_DISABLE,
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.priority = 1,
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.hardware_event = false,
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.client_managed = false,
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.offload_channel = false,
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},
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};
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static struct mhi_controller_config ath11k_mhi_config_qca6390 = {
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.max_channels = 128,
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.timeout_ms = 2000,
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.use_bounce_buf = false,
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.buf_len = 8192,
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.num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390),
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.ch_cfg = ath11k_mhi_channels_qca6390,
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.num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390),
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.event_cfg = ath11k_mhi_events_qca6390,
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};
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static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = {
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{
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.num = 0,
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.name = "LOOPBACK",
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.num_elements = 32,
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.event_ring = 1,
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.dir = DMA_TO_DEVICE,
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.ee_mask = 0x14,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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},
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{
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.num = 1,
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.name = "LOOPBACK",
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.num_elements = 32,
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.event_ring = 1,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = 0x14,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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},
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{
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.num = 20,
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.name = "IPCR",
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.num_elements = 32,
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.event_ring = 1,
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.dir = DMA_TO_DEVICE,
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.ee_mask = 0x14,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = false,
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},
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{
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.num = 21,
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.name = "IPCR",
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.num_elements = 32,
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.event_ring = 1,
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.dir = DMA_FROM_DEVICE,
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.ee_mask = 0x14,
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.pollcfg = 0,
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.doorbell = MHI_DB_BRST_DISABLE,
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.lpm_notify = false,
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.offload_channel = false,
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.doorbell_mode_switch = false,
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.auto_queue = true,
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},
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};
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static struct mhi_event_config ath11k_mhi_events_qcn9074[] = {
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{
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.num_elements = 32,
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.irq_moderation_ms = 0,
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.irq = 1,
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.data_type = MHI_ER_CTRL,
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.mode = MHI_DB_BRST_DISABLE,
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.hardware_event = false,
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.client_managed = false,
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.offload_channel = false,
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},
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{
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.num_elements = 256,
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.irq_moderation_ms = 1,
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.irq = 2,
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.mode = MHI_DB_BRST_DISABLE,
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.priority = 1,
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.hardware_event = false,
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.client_managed = false,
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.offload_channel = false,
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},
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};
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static struct mhi_controller_config ath11k_mhi_config_qcn9074 = {
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.max_channels = 30,
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.timeout_ms = 10000,
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.use_bounce_buf = false,
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.buf_len = 0,
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.num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074),
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.ch_cfg = ath11k_mhi_channels_qcn9074,
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.num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074),
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.event_cfg = ath11k_mhi_events_qcn9074,
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};
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void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab)
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{
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u32 val;
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val = ath11k_pcic_read32(ab, MHISTATUS);
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ath11k_dbg(ab, ATH11K_DBG_PCI, "mhistatus 0x%x\n", val);
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/* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS
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* has SYSERR bit set and thus need to set MHICTRL_RESET
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* to clear SYSERR.
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*/
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ath11k_pcic_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
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mdelay(10);
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}
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static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab)
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{
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ath11k_pcic_write32(ab, PCIE_TXVECDB, 0);
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}
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static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab)
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{
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ath11k_pcic_write32(ab, PCIE_TXVECSTATUS, 0);
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}
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static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab)
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{
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ath11k_pcic_write32(ab, PCIE_RXVECDB, 0);
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}
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static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab)
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{
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ath11k_pcic_write32(ab, PCIE_RXVECSTATUS, 0);
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}
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void ath11k_mhi_clear_vector(struct ath11k_base *ab)
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{
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ath11k_mhi_reset_txvecdb(ab);
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ath11k_mhi_reset_txvecstatus(ab);
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ath11k_mhi_reset_rxvecdb(ab);
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ath11k_mhi_reset_rxvecstatus(ab);
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}
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static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci)
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{
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struct ath11k_base *ab = ab_pci->ab;
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u32 user_base_data, base_vector;
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int ret, num_vectors, i;
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int *irq;
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unsigned int msi_data;
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ret = ath11k_pcic_get_user_msi_assignment(ab, "MHI", &num_vectors,
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&user_base_data, &base_vector);
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if (ret)
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return ret;
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ath11k_dbg(ab, ATH11K_DBG_PCI, "num_vectors %d base_vector %d\n",
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num_vectors, base_vector);
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irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL);
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if (!irq)
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return -ENOMEM;
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for (i = 0; i < num_vectors; i++) {
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msi_data = base_vector;
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if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
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msi_data += i;
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irq[i] = ath11k_pci_get_msi_irq(ab, msi_data);
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}
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ab_pci->mhi_ctrl->irq = irq;
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ab_pci->mhi_ctrl->nr_irqs = num_vectors;
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return 0;
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}
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static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
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{
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return 0;
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}
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static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
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{
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}
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static char *ath11k_mhi_op_callback_to_str(enum mhi_callback reason)
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{
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switch (reason) {
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case MHI_CB_IDLE:
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return "MHI_CB_IDLE";
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case MHI_CB_PENDING_DATA:
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return "MHI_CB_PENDING_DATA";
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case MHI_CB_LPM_ENTER:
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return "MHI_CB_LPM_ENTER";
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case MHI_CB_LPM_EXIT:
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return "MHI_CB_LPM_EXIT";
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case MHI_CB_EE_RDDM:
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return "MHI_CB_EE_RDDM";
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case MHI_CB_EE_MISSION_MODE:
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return "MHI_CB_EE_MISSION_MODE";
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case MHI_CB_SYS_ERROR:
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return "MHI_CB_SYS_ERROR";
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case MHI_CB_FATAL_ERROR:
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return "MHI_CB_FATAL_ERROR";
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case MHI_CB_BW_REQ:
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return "MHI_CB_BW_REQ";
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default:
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return "UNKNOWN";
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}
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};
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static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
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enum mhi_callback cb)
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{
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struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
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ath11k_dbg(ab, ATH11K_DBG_BOOT, "notify status reason %s\n",
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ath11k_mhi_op_callback_to_str(cb));
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switch (cb) {
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case MHI_CB_SYS_ERROR:
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ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
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break;
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case MHI_CB_EE_RDDM:
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if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags)))
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queue_work(ab->workqueue_aux, &ab->reset_work);
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break;
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default:
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break;
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}
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}
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static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
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void __iomem *addr,
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u32 *out)
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{
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*out = readl(addr);
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return 0;
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}
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static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
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void __iomem *addr,
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u32 val)
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{
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writel(val, addr);
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}
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static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl)
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{
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struct device_node *np;
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struct resource res;
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int ret;
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np = of_find_node_by_type(NULL, "memory");
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if (!np)
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return -ENOENT;
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ret = of_address_to_resource(np, 0, &res);
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of_node_put(np);
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if (ret)
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return ret;
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mhi_ctrl->iova_start = res.start + 0x1000000;
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mhi_ctrl->iova_stop = res.end;
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return 0;
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}
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int ath11k_mhi_register(struct ath11k_pci *ab_pci)
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{
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struct ath11k_base *ab = ab_pci->ab;
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struct mhi_controller *mhi_ctrl;
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struct mhi_controller_config *ath11k_mhi_config;
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int ret;
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mhi_ctrl = mhi_alloc_controller();
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if (!mhi_ctrl)
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return -ENOMEM;
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ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE,
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ab_pci->amss_path,
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sizeof(ab_pci->amss_path));
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ab_pci->mhi_ctrl = mhi_ctrl;
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mhi_ctrl->cntrl_dev = ab->dev;
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mhi_ctrl->fw_image = ab_pci->amss_path;
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mhi_ctrl->regs = ab->mem;
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mhi_ctrl->reg_len = ab->mem_len;
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ret = ath11k_mhi_get_msi(ab_pci);
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if (ret) {
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ath11k_err(ab, "failed to get msi for mhi\n");
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goto free_controller;
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}
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if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
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mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
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if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) {
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ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl);
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if (ret < 0)
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goto free_controller;
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} else {
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mhi_ctrl->iova_start = 0;
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mhi_ctrl->iova_stop = 0xFFFFFFFF;
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}
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mhi_ctrl->rddm_size = RDDM_DUMP_SIZE;
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mhi_ctrl->sbl_size = SZ_512K;
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mhi_ctrl->seg_len = SZ_512K;
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mhi_ctrl->fbc_download = true;
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mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get;
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mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put;
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mhi_ctrl->status_cb = ath11k_mhi_op_status_cb;
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mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
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mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
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switch (ab->hw_rev) {
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case ATH11K_HW_QCN9074_HW10:
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ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
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break;
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case ATH11K_HW_QCA6390_HW20:
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case ATH11K_HW_WCN6855_HW20:
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case ATH11K_HW_WCN6855_HW21:
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ath11k_mhi_config = &ath11k_mhi_config_qca6390;
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break;
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default:
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ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n",
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ab->hw_rev);
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ret = -EINVAL;
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goto free_controller;
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}
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ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config);
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if (ret) {
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ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
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goto free_controller;
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}
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return 0;
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free_controller:
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mhi_free_controller(mhi_ctrl);
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ab_pci->mhi_ctrl = NULL;
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return ret;
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}
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void ath11k_mhi_unregister(struct ath11k_pci *ab_pci)
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{
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struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
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mhi_unregister_controller(mhi_ctrl);
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kfree(mhi_ctrl->irq);
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mhi_free_controller(mhi_ctrl);
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}
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int ath11k_mhi_start(struct ath11k_pci *ab_pci)
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{
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struct ath11k_base *ab = ab_pci->ab;
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int ret;
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ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;
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ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
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if (ret) {
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ath11k_warn(ab, "failed to prepare mhi: %d", ret);
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return ret;
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}
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ret = mhi_sync_power_up(ab_pci->mhi_ctrl);
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if (ret) {
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ath11k_warn(ab, "failed to power up mhi: %d", ret);
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return ret;
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}
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return 0;
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}
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void ath11k_mhi_stop(struct ath11k_pci *ab_pci)
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{
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mhi_power_down(ab_pci->mhi_ctrl, true);
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mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
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}
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int ath11k_mhi_suspend(struct ath11k_pci *ab_pci)
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{
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struct ath11k_base *ab = ab_pci->ab;
|
|
int ret;
|
|
|
|
ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
|
|
if (ret) {
|
|
ath11k_warn(ab, "failed to suspend mhi: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ath11k_mhi_resume(struct ath11k_pci *ab_pci)
|
|
{
|
|
struct ath11k_base *ab = ab_pci->ab;
|
|
int ret;
|
|
|
|
/* Do force MHI resume as some devices like QCA6390, WCN6855
|
|
* are not in M3 state but they are functional. So just ignore
|
|
* the MHI state while resuming.
|
|
*/
|
|
ret = mhi_pm_resume_force(ab_pci->mhi_ctrl);
|
|
if (ret) {
|
|
ath11k_warn(ab, "failed to resume mhi: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|