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8eed1db1ad
The g12a use fractional parameter of 17 useful bits. At the moment, this parameter in encoded using u16 value. Use this opportunity to switch all the pll to parameter to unsigned int. This should save us some annoying trouble shooting when and m and n field eventually grow as well. This patch also introduce pll multiplier range. On the g12a, the hifi and gp0 plls are able to lock as long as the following condition is met: 55 <= m/n <= 255. The param table describing this would be huge which is a waste of memory. Using ranges, we can save memory. Ranges also help find the best pll parameter significantly faster since we don't have to try all the possible settings. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [jbrunet: fixed fix pll settings calculation with arm32] Link: https://lkml.kernel.org/r/20190201145345.6795-2-jbrunet@baylibre.com
49 lines
941 B
C
49 lines
941 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __MESON_CLK_PLL_H
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#define __MESON_CLK_PLL_H
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "parm.h"
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struct pll_params_table {
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unsigned int m;
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unsigned int n;
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};
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struct pll_mult_range {
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unsigned int min;
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unsigned int max;
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};
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#define PLL_PARAMS(_m, _n) \
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{ \
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.m = (_m), \
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.n = (_n), \
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}
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#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
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struct meson_clk_pll_data {
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struct parm en;
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struct parm m;
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struct parm n;
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struct parm frac;
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struct parm l;
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struct parm rst;
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const struct reg_sequence *init_regs;
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unsigned int init_count;
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const struct pll_params_table *table;
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const struct pll_mult_range *range;
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u8 flags;
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};
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extern const struct clk_ops meson_clk_pll_ro_ops;
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extern const struct clk_ops meson_clk_pll_ops;
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#endif /* __MESON_CLK_PLL_H */
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