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2424f54902
If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 5249 QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
269 lines
9.1 KiB
C
269 lines
9.1 KiB
C
/****************************************************************************/
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/*
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* m5249sim.h -- ColdFire 5249 System Integration Module support.
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*
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* (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
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*/
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/****************************************************************************/
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#ifndef m5249sim_h
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#define m5249sim_h
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/****************************************************************************/
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#define CPU_NAME "COLDFIRE(m5249)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK (MCF_CLK / 2)
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#include <asm/m52xxacr.h>
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/*
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* The 5249 has a second MBAR region, define its address.
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*/
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#define MCF_MBAR2 0x80000000
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/*
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* Define the 5249 SIM register set addresses.
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*/
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#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
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#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
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#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
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#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
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#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
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#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
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#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
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#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
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#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
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#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
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#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
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#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
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#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
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#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
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#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
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#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
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#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
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#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
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#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
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#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
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#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
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#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
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#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
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#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
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#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
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#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
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#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
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#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
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#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
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#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
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#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
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#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
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#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
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#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
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#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
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#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
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#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
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#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
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#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
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/*
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* Timer module.
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*/
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#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
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#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
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/*
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* UART module.
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*/
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#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
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#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
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/*
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* QSPI module.
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*/
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#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
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#define MCFQSPI_SIZE 0x40 /* Register set size */
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#define MCFQSPI_CS0 29
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#define MCFQSPI_CS1 24
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#define MCFQSPI_CS2 21
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#define MCFQSPI_CS3 22
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/*
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* DMA unit base addresses.
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*/
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#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
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#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
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#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
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#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
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/*
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* Some symbol defines for the above...
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*/
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#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
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#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
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#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
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#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
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#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
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#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
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#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
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#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
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#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
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#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
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#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
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#define MCF_IRQ_UART0 73 /* UART0 */
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#define MCF_IRQ_UART1 74 /* UART1 */
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/*
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* General purpose IO registers (in MBAR2).
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*/
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#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
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#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
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#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
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#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
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#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
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#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
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#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
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#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
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#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
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#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
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#define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */
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#define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */
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#define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */
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#define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */
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#define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */
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#define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */
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#define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */
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#define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */
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#define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */
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#define MCFSIM2_DMAROUTE 0x188 /* DMA routing */
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#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */
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#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */
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/*
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* Define the base interrupt for the second interrupt controller.
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* We set it to 128, out of the way of the base interrupts, and plenty
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* of room for its 64 interrupts.
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*/
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#define MCFINTC2_VECBASE 128
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#define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32)
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#define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33)
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#define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34)
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#define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35)
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#define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36)
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#define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37)
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#define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38)
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#define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39)
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PIN_MAX 64
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#define MCFGPIO_IRQ_MAX -1
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#define MCFGPIO_IRQ_VECBASE -1
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/****************************************************************************/
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#ifdef __ASSEMBLER__
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/*
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* The M5249C3 board needs a little help getting all its SIM devices
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* initialized at kernel start time. dBUG doesn't set much up, so
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* we need to do it manually.
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*/
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.macro m5249c3_setup
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/*
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* Set MBAR1 and MBAR2, just incase they are not set.
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*/
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movel #0x10000001,%a0
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movec %a0,%MBAR /* map MBAR region */
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subql #1,%a0 /* get MBAR address in a0 */
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movel #0x80000001,%a1
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movec %a1,#3086 /* map MBAR2 region */
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subql #1,%a1 /* get MBAR2 address in a1 */
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/*
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* Move secondary interrupts to their base (128).
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*/
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moveb #MCFINTC2_VECBASE,%d0
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moveb %d0,0x16b(%a1) /* interrupt base register */
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/*
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* Work around broken CSMR0/DRAM vector problem.
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*/
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movel #0x001F0021,%d0 /* disable C/I bit */
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movel %d0,0x84(%a0) /* set CSMR0 */
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/*
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* Disable the PLL firstly. (Who knows what state it is
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* in here!).
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*/
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movel 0x180(%a1),%d0 /* get current PLL value */
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andl #0xfffffffe,%d0 /* PLL bypass first */
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movel %d0,0x180(%a1) /* set PLL register */
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nop
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#if CONFIG_CLOCK_FREQ == 140000000
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/*
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* Set initial clock frequency. This assumes M5249C3 board
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* is fitted with 11.2896MHz crystal. It will program the
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* PLL for 140MHz. Lets go fast :-)
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*/
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movel #0x125a40f0,%d0 /* set for 140MHz */
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movel %d0,0x180(%a1) /* set PLL register */
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orl #0x1,%d0
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movel %d0,0x180(%a1) /* set PLL register */
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#endif
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/*
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* Setup CS1 for ethernet controller.
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* (Setup as per M5249C3 doco).
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*/
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movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
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movel %d0,0x8c(%a0)
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movel #0x001f0021,%d0 /* CS1 size of 1Mb */
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movel %d0,0x90(%a0)
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movew #0x0080,%d0 /* CS1 = 16bit port, AA */
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movew %d0,0x96(%a0)
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/*
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* Setup CS2 for IDE interface.
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*/
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movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
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movel %d0,0x98(%a0)
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movel #0x001f0001,%d0 /* CS2 size of 1MB */
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movel %d0,0x9c(%a0)
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movew #0x0080,%d0 /* CS2 = 16bit, TA */
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movew %d0,0xa2(%a0)
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movel #0x00107000,%d0 /* IDEconfig1 */
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movel %d0,0x18c(%a1)
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movel #0x000c0400,%d0 /* IDEconfig2 */
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movel %d0,0x190(%a1)
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movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
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orl %d0,0xc(%a1) /* function GPIO19 */
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orl %d0,0x8(%a1) /* enable GPIO19 as output */
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orl %d0,0x4(%a1) /* de-assert IDE reset */
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.endm
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#define PLATFORM_SETUP m5249c3_setup
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#endif /* __ASSEMBLER__ */
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/****************************************************************************/
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#endif /* m5249sim_h */
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