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4917e498c6
The ARR register is cleared unconditionally upon probing, after the maximum
value has been read. This initial condition is rather not intuitive, when
considering the counter child driver. It rather expects the maximum value
by default:
- The counter interface shows a zero value by default for 'ceiling'
attribute.
- Enabling the counter without any prior configuration makes it doesn't
count.
The reset value of ARR register is the maximum. So Choice here
is to backup it, and restore it then, instead of clearing its value.
It also fixes the initial condition seen by the counter driver.
Fixes: d0f949e220
("mfd: Add STM32 Timers driver")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Acked-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
294 lines
7.7 KiB
C
294 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2016
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* Author: Benjamin Gaignard <benjamin.gaignard@st.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/mfd/stm32-timers.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/reset.h>
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#define STM32_TIMERS_MAX_REGISTERS 0x3fc
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/* DIER register DMA enable bits */
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static const u32 stm32_timers_dier_dmaen[STM32_TIMERS_MAX_DMAS] = {
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TIM_DIER_CC1DE,
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TIM_DIER_CC2DE,
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TIM_DIER_CC3DE,
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TIM_DIER_CC4DE,
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TIM_DIER_UIE,
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TIM_DIER_TDE,
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TIM_DIER_COMDE
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};
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static void stm32_timers_dma_done(void *p)
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{
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struct stm32_timers_dma *dma = p;
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struct dma_tx_state state;
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enum dma_status status;
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status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state);
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if (status == DMA_COMPLETE)
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complete(&dma->completion);
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}
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/**
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* stm32_timers_dma_burst_read - Read from timers registers using DMA.
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*
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* Read from STM32 timers registers using DMA on a single event.
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* @dev: reference to stm32_timers MFD device
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* @buf: DMA'able destination buffer
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* @id: stm32_timers_dmas event identifier (ch[1..4], up, trig or com)
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* @reg: registers start offset for DMA to read from (like CCRx for capture)
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* @num_reg: number of registers to read upon each DMA request, starting @reg.
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* @bursts: number of bursts to read (e.g. like two for pwm period capture)
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* @tmo_ms: timeout (milliseconds)
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*/
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int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
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enum stm32_timers_dmas id, u32 reg,
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unsigned int num_reg, unsigned int bursts,
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unsigned long tmo_ms)
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{
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struct stm32_timers *ddata = dev_get_drvdata(dev);
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unsigned long timeout = msecs_to_jiffies(tmo_ms);
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struct regmap *regmap = ddata->regmap;
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struct stm32_timers_dma *dma = &ddata->dma;
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size_t len = num_reg * bursts * sizeof(u32);
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struct dma_async_tx_descriptor *desc;
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struct dma_slave_config config;
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dma_cookie_t cookie;
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dma_addr_t dma_buf;
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u32 dbl, dba;
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long err;
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int ret;
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/* Sanity check */
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if (id < STM32_TIMERS_DMA_CH1 || id >= STM32_TIMERS_MAX_DMAS)
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return -EINVAL;
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if (!num_reg || !bursts || reg > STM32_TIMERS_MAX_REGISTERS ||
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(reg + num_reg * sizeof(u32)) > STM32_TIMERS_MAX_REGISTERS)
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return -EINVAL;
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if (!dma->chans[id])
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return -ENODEV;
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mutex_lock(&dma->lock);
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/* Select DMA channel in use */
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dma->chan = dma->chans[id];
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dma_buf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
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if (dma_mapping_error(dev, dma_buf)) {
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ret = -ENOMEM;
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goto unlock;
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}
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/* Prepare DMA read from timer registers, using DMA burst mode */
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memset(&config, 0, sizeof(config));
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config.src_addr = (dma_addr_t)dma->phys_base + TIM_DMAR;
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config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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ret = dmaengine_slave_config(dma->chan, &config);
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if (ret)
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goto unmap;
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desc = dmaengine_prep_slave_single(dma->chan, dma_buf, len,
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DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
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if (!desc) {
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ret = -EBUSY;
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goto unmap;
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}
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desc->callback = stm32_timers_dma_done;
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desc->callback_param = dma;
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cookie = dmaengine_submit(desc);
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ret = dma_submit_error(cookie);
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if (ret)
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goto dma_term;
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reinit_completion(&dma->completion);
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dma_async_issue_pending(dma->chan);
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/* Setup and enable timer DMA burst mode */
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dbl = FIELD_PREP(TIM_DCR_DBL, bursts - 1);
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dba = FIELD_PREP(TIM_DCR_DBA, reg >> 2);
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ret = regmap_write(regmap, TIM_DCR, dbl | dba);
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if (ret)
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goto dma_term;
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/* Clear pending flags before enabling DMA request */
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ret = regmap_write(regmap, TIM_SR, 0);
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if (ret)
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goto dcr_clr;
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ret = regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id],
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stm32_timers_dier_dmaen[id]);
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if (ret)
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goto dcr_clr;
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err = wait_for_completion_interruptible_timeout(&dma->completion,
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timeout);
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if (err == 0)
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ret = -ETIMEDOUT;
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else if (err < 0)
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ret = err;
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regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id], 0);
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regmap_write(regmap, TIM_SR, 0);
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dcr_clr:
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regmap_write(regmap, TIM_DCR, 0);
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dma_term:
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dmaengine_terminate_all(dma->chan);
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unmap:
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dma_unmap_single(dev, dma_buf, len, DMA_FROM_DEVICE);
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unlock:
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dma->chan = NULL;
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mutex_unlock(&dma->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(stm32_timers_dma_burst_read);
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static const struct regmap_config stm32_timers_regmap_cfg = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = sizeof(u32),
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.max_register = STM32_TIMERS_MAX_REGISTERS,
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};
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static void stm32_timers_get_arr_size(struct stm32_timers *ddata)
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{
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u32 arr;
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/* Backup ARR to restore it after getting the maximum value */
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regmap_read(ddata->regmap, TIM_ARR, &arr);
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/*
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* Only the available bits will be written so when readback
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* we get the maximum value of auto reload register
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*/
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regmap_write(ddata->regmap, TIM_ARR, ~0L);
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regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr);
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regmap_write(ddata->regmap, TIM_ARR, arr);
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}
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static int stm32_timers_dma_probe(struct device *dev,
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struct stm32_timers *ddata)
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{
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int i;
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int ret = 0;
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char name[4];
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init_completion(&ddata->dma.completion);
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mutex_init(&ddata->dma.lock);
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/* Optional DMA support: get valid DMA channel(s) or NULL */
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for (i = STM32_TIMERS_DMA_CH1; i <= STM32_TIMERS_DMA_CH4; i++) {
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snprintf(name, ARRAY_SIZE(name), "ch%1d", i + 1);
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ddata->dma.chans[i] = dma_request_chan(dev, name);
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}
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ddata->dma.chans[STM32_TIMERS_DMA_UP] = dma_request_chan(dev, "up");
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ddata->dma.chans[STM32_TIMERS_DMA_TRIG] = dma_request_chan(dev, "trig");
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ddata->dma.chans[STM32_TIMERS_DMA_COM] = dma_request_chan(dev, "com");
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for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++) {
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if (IS_ERR(ddata->dma.chans[i])) {
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/* Save the first error code to return */
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if (PTR_ERR(ddata->dma.chans[i]) != -ENODEV && !ret)
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ret = PTR_ERR(ddata->dma.chans[i]);
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ddata->dma.chans[i] = NULL;
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}
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}
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return ret;
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}
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static void stm32_timers_dma_remove(struct device *dev,
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struct stm32_timers *ddata)
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{
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int i;
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for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++)
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if (ddata->dma.chans[i])
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dma_release_channel(ddata->dma.chans[i]);
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}
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static int stm32_timers_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct stm32_timers *ddata;
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struct resource *res;
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void __iomem *mmio;
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int ret;
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ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
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if (!ddata)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mmio = devm_ioremap_resource(dev, res);
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if (IS_ERR(mmio))
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return PTR_ERR(mmio);
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/* Timer physical addr for DMA */
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ddata->dma.phys_base = res->start;
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ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio,
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&stm32_timers_regmap_cfg);
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if (IS_ERR(ddata->regmap))
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return PTR_ERR(ddata->regmap);
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ddata->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(ddata->clk))
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return PTR_ERR(ddata->clk);
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stm32_timers_get_arr_size(ddata);
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ret = stm32_timers_dma_probe(dev, ddata);
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if (ret) {
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stm32_timers_dma_remove(dev, ddata);
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return ret;
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}
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platform_set_drvdata(pdev, ddata);
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ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
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if (ret)
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stm32_timers_dma_remove(dev, ddata);
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return ret;
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}
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static int stm32_timers_remove(struct platform_device *pdev)
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{
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struct stm32_timers *ddata = platform_get_drvdata(pdev);
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/*
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* Don't use devm_ here: enfore of_platform_depopulate() happens before
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* DMA are released, to avoid race on DMA.
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*/
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of_platform_depopulate(&pdev->dev);
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stm32_timers_dma_remove(&pdev->dev, ddata);
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return 0;
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}
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static const struct of_device_id stm32_timers_of_match[] = {
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{ .compatible = "st,stm32-timers", },
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{ /* end node */ },
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};
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MODULE_DEVICE_TABLE(of, stm32_timers_of_match);
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static struct platform_driver stm32_timers_driver = {
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.probe = stm32_timers_probe,
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.remove = stm32_timers_remove,
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.driver = {
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.name = "stm32-timers",
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.of_match_table = stm32_timers_of_match,
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},
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};
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module_platform_driver(stm32_timers_driver);
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MODULE_DESCRIPTION("STMicroelectronics STM32 Timers");
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MODULE_LICENSE("GPL v2");
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