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b99afae139
The naked attribute is known to confuse some old gcc versions when
function arguments aren't explicitly listed as inline assembly operands
despite the gcc documentation. That resulted in commit 9a40ac8615
("ARM: 6164/1: Add kto and kfrom to input operands list.").
Yet that commit has problems of its own by having assembly operand
constraints completely wrong. If the generated code has been OK since
then, it is due to luck rather than correctness. So this patch also
provides proper assembly operand constraints, and removes two instances
of redundant register usages in the implementation while at it.
Inspection of the generated code with this patch doesn't show any
obvious quality degradation either, so not relying on __naked at all
will make the code less fragile, and avoid some issues with clang.
The only remaining __naked instances (excluding the kprobes test cases)
are exynos_pm_power_up_setup(), tc2_pm_power_up_setup() and
cci_enable_port_for_self(. But in the first two cases, only the function
address is used by the compiler with no chance of inlining it by
mistake, and the third case is called from assembly code only. And the
fact that no stack is available when the corresponding code is executed
does warrant the __naked usage in those cases.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
87 lines
2.3 KiB
C
87 lines
2.3 KiB
C
/*
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* linux/arch/arm/mm/copypage-v4wt.S
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*
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* Copyright (C) 1995-1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is for CPUs with a writethrough cache and 'flush ID cache' is
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* the only supported cache operation.
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*/
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#include <linux/init.h>
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#include <linux/highmem.h>
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/*
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* ARMv4 optimised copy_user_highpage
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*
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* Since we have writethrough caches, we don't have to worry about
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* dirty data in the cache. However, we do have to ensure that
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* subsequent reads are up to date.
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*/
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static void v4wt_copy_user_page(void *kto, const void *kfrom)
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{
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int tmp;
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asm volatile ("\
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ldmia %1!, {r3, r4, ip, lr} @ 4\n\
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1: stmia %0!, {r3, r4, ip, lr} @ 4\n\
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ldmia %1!, {r3, r4, ip, lr} @ 4+1\n\
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stmia %0!, {r3, r4, ip, lr} @ 4\n\
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ldmia %1!, {r3, r4, ip, lr} @ 4\n\
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stmia %0!, {r3, r4, ip, lr} @ 4\n\
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ldmia %1!, {r3, r4, ip, lr} @ 4\n\
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subs %2, %2, #1 @ 1\n\
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stmia %0!, {r3, r4, ip, lr} @ 4\n\
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ldmneia %1!, {r3, r4, ip, lr} @ 4\n\
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bne 1b @ 1\n\
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mcr p15, 0, %2, c7, c7, 0 @ flush ID cache"
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: "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)
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: "2" (PAGE_SIZE / 64)
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: "r3", "r4", "ip", "lr");
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}
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void v4wt_copy_user_highpage(struct page *to, struct page *from,
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unsigned long vaddr, struct vm_area_struct *vma)
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{
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void *kto, *kfrom;
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kto = kmap_atomic(to);
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kfrom = kmap_atomic(from);
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v4wt_copy_user_page(kto, kfrom);
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kunmap_atomic(kfrom);
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kunmap_atomic(kto);
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}
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/*
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* ARMv4 optimised clear_user_page
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*
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* Same story as above.
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*/
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void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr)
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{
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void *ptr, *kaddr = kmap_atomic(page);
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asm volatile("\
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mov r1, %2 @ 1\n\
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mov r2, #0 @ 1\n\
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mov r3, #0 @ 1\n\
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mov ip, #0 @ 1\n\
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mov lr, #0 @ 1\n\
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1: stmia %0!, {r2, r3, ip, lr} @ 4\n\
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stmia %0!, {r2, r3, ip, lr} @ 4\n\
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stmia %0!, {r2, r3, ip, lr} @ 4\n\
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stmia %0!, {r2, r3, ip, lr} @ 4\n\
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subs r1, r1, #1 @ 1\n\
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bne 1b @ 1\n\
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mcr p15, 0, r2, c7, c7, 0 @ flush ID cache"
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: "=r" (ptr)
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: "0" (kaddr), "I" (PAGE_SIZE / 64)
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: "r1", "r2", "r3", "ip", "lr");
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kunmap_atomic(kaddr);
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}
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struct cpu_user_fns v4wt_user_fns __initdata = {
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.cpu_clear_user_highpage = v4wt_clear_user_highpage,
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.cpu_copy_user_highpage = v4wt_copy_user_highpage,
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};
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