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While CXL builds upon the PCI software model for enumeration and endpoint control, a static platform component is required to bootstrap the CXL memory layout. Similar to how ACPI identifies root-level PCI memory resources, ACPI data enumerates the address space and interleave configuration for CXL Memory. In addition to identifying host bridges, ACPI is responsible for enumerating the CXL memory space that can be addressed by downstream decoders. This is similar to the requirement for ACPI to publish resources via the _CRS method for PCI host bridges. Specifically, ACPI publishes a table, CXL Early Discovery Table (CEDT), which includes a list of CXL Memory resources, CXL Fixed Memory Window Structures (CFMWS). For now, introduce the core infrastructure for a cxl_port hierarchy starting with a root level anchor represented by the ACPI0017 device. Follow on changes model support for the configurable decode capabilities of cxl_port instances, i.e. CXL switch support. Co-developed-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Alison Schofield <alison.schofield@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/162325449515.2293126.15303270193010154608.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
52 lines
1.3 KiB
ReStructuredText
52 lines
1.3 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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.. include:: <isonum.txt>
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===================================
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Compute Express Link Memory Devices
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===================================
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A Compute Express Link Memory Device is a CXL component that implements the
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CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
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or both. It is enumerated as a PCI device for configuration and passing
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messages over an MMIO mailbox. Its contribution to the System Physical
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Address space is handled via HDM (Host Managed Device Memory) decoders
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that optionally define a device's contribution to an interleaved address
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range across multiple devices underneath a host-bridge or interleaved
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across host-bridges.
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Driver Infrastructure
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=====================
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This section covers the driver infrastructure for a CXL memory device.
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CXL Memory Device
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-----------------
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.. kernel-doc:: drivers/cxl/pci.c
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:doc: cxl pci
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.. kernel-doc:: drivers/cxl/pci.c
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:internal:
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CXL Core
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--------
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.. kernel-doc:: drivers/cxl/cxl.h
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:doc: cxl objects
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.. kernel-doc:: drivers/cxl/cxl.h
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:internal:
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.. kernel-doc:: drivers/cxl/core.c
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:doc: cxl core
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External Interfaces
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===================
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CXL IOCTL Interface
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-------------------
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.. kernel-doc:: include/uapi/linux/cxl_mem.h
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:doc: UAPI
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.. kernel-doc:: include/uapi/linux/cxl_mem.h
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:internal:
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