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fade9c2c6e
Although naming across the codebase isn't that consistent, it tends to follow certain patterns. Moreover, the term "flush" isn't defined in the Arm Architecture reference manual, and might be interpreted to mean clean, invalidate, or both for a cache. Rename arm64-internal functions to make the naming internally consistent, as well as making it consistent with the Arm ARM, by specifying whether it applies to the instruction, data, or both caches, whether the operation is a clean, invalidate, or both. Also specify which point the operation applies to, i.e., to the point of unification (PoU), coherency (PoC), or persistence (PoP). This commit applies the following sed transformation to all files under arch/arm64: "s/\b__flush_cache_range\b/caches_clean_inval_pou_macro/g;"\ "s/\b__flush_icache_range\b/caches_clean_inval_pou/g;"\ "s/\binvalidate_icache_range\b/icache_inval_pou/g;"\ "s/\b__flush_dcache_area\b/dcache_clean_inval_poc/g;"\ "s/\b__inval_dcache_area\b/dcache_inval_poc/g;"\ "s/__clean_dcache_area_poc\b/dcache_clean_poc/g;"\ "s/\b__clean_dcache_area_pop\b/dcache_clean_pop/g;"\ "s/\b__clean_dcache_area_pou\b/dcache_clean_pou/g;"\ "s/\b__flush_cache_user_range\b/caches_clean_inval_user_pou/g;"\ "s/\b__flush_icache_all\b/icache_inval_all_pou/g;" Note that __clean_dcache_area_poc is deliberately missing a word boundary check at the beginning in order to match the efistub symbols in image-vars.h. Also note that, despite its name, __flush_icache_range operates on both instruction and data caches. The name change here reflects that. No functional change intended. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Fuad Tabba <tabba@google.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20210524083001.2586635-19-tabba@google.com Signed-off-by: Will Deacon <will@kernel.org>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Spin Table SMP initialisation
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*
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* Copyright (C) 2013 ARM Ltd.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <asm/cacheflush.h>
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#include <asm/cpu_ops.h>
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#include <asm/cputype.h>
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#include <asm/io.h>
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#include <asm/smp_plat.h>
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extern void secondary_holding_pen(void);
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volatile unsigned long __section(".mmuoff.data.read")
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secondary_holding_pen_release = INVALID_HWID;
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static phys_addr_t cpu_release_addr[NR_CPUS];
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/*
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* Write secondary_holding_pen_release in a way that is guaranteed to be
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* visible to all observers, irrespective of whether they're taking part
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* in coherency or not. This is necessary for the hotplug code to work
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* reliably.
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*/
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static void write_pen_release(u64 val)
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{
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void *start = (void *)&secondary_holding_pen_release;
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unsigned long size = sizeof(secondary_holding_pen_release);
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secondary_holding_pen_release = val;
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dcache_clean_inval_poc((unsigned long)start, (unsigned long)start + size);
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}
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static int smp_spin_table_cpu_init(unsigned int cpu)
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{
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struct device_node *dn;
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int ret;
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dn = of_get_cpu_node(cpu, NULL);
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if (!dn)
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return -ENODEV;
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/*
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* Determine the address from which the CPU is polling.
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*/
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ret = of_property_read_u64(dn, "cpu-release-addr",
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&cpu_release_addr[cpu]);
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if (ret)
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pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
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cpu);
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of_node_put(dn);
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return ret;
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}
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static int smp_spin_table_cpu_prepare(unsigned int cpu)
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{
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__le64 __iomem *release_addr;
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phys_addr_t pa_holding_pen = __pa_symbol(function_nocfi(secondary_holding_pen));
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if (!cpu_release_addr[cpu])
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return -ENODEV;
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/*
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* The cpu-release-addr may or may not be inside the linear mapping.
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* As ioremap_cache will either give us a new mapping or reuse the
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* existing linear mapping, we can use it to cover both cases. In
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* either case the memory will be MT_NORMAL.
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*/
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release_addr = ioremap_cache(cpu_release_addr[cpu],
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sizeof(*release_addr));
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if (!release_addr)
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return -ENOMEM;
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/*
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* We write the release address as LE regardless of the native
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* endianness of the kernel. Therefore, any boot-loaders that
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* read this address need to convert this address to the
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* boot-loader's endianness before jumping. This is mandated by
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* the boot protocol.
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*/
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writeq_relaxed(pa_holding_pen, release_addr);
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dcache_clean_inval_poc((__force unsigned long)release_addr,
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(__force unsigned long)release_addr +
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sizeof(*release_addr));
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/*
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* Send an event to wake up the secondary CPU.
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*/
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sev();
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iounmap(release_addr);
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return 0;
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}
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static int smp_spin_table_cpu_boot(unsigned int cpu)
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{
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/*
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* Update the pen release flag.
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*/
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write_pen_release(cpu_logical_map(cpu));
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/*
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* Send an event, causing the secondaries to read pen_release.
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*/
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sev();
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return 0;
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}
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const struct cpu_operations smp_spin_table_ops = {
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.name = "spin-table",
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.cpu_init = smp_spin_table_cpu_init,
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.cpu_prepare = smp_spin_table_cpu_prepare,
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.cpu_boot = smp_spin_table_cpu_boot,
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};
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