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3427fa5b32
Add YAML DT schema for the AMD AXI w1 host IP. This hardware guarantees protocol timing for driving off-board devices such as thermal sensors, proms, etc using the 1wire protocol. The IP has a register to detect hardware version and so the binding does not have an explicit version number. Add MAINTAINERS entry for DT schema. Co-developed-by: Thomas Delev <thomas.delev@amd.com> Signed-off-by: Thomas Delev <thomas.delev@amd.com> Signed-off-by: Kris Chaplin <kris.chaplin@amd.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231107180814.615933-2-kris.chaplin@amd.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
44 lines
811 B
YAML
44 lines
811 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: AMD AXI 1-wire bus host for programmable logic
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maintainers:
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- Kris Chaplin <kris.chaplin@amd.com>
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properties:
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compatible:
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const: amd,axi-1wire-host
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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onewire@a0000000 {
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compatible = "amd,axi-1wire-host";
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reg = <0xa0000000 0x10000>;
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clocks = <&zynqmp_clk 0x47>;
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interrupts = <GIC_SPI 0x59 IRQ_TYPE_LEVEL_HIGH>;
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};
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...
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