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1583052d11
AML uses SystemMemory opregions to allow AML handlers to access MMIO registers of, e.g., GPIO controllers, or access reserved regions of memory that are owned by the firmware. Currently, we also allow AML access to memory that is owned by the kernel and mapped via the linear region, which does not seem to be supported by a valid use case, and exposes the kernel's internal state to AML methods that may be buggy and exploitable. On arm64, ACPI support requires booting in EFI mode, and so we can cross reference the requested region against the EFI memory map, rather than just do a minimal check on the first page. So let's only permit regions to be remapped by the ACPI core if - they don't appear in the EFI memory map at all (which is the case for most MMIO), or - they are covered by a single region in the EFI memory map, which is not of a type that describes memory that is given to the kernel at boot. Reported-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Link: https://lore.kernel.org/r/20200626155832.2323789-2-ardb@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
157 lines
4.6 KiB
C
157 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013-2014, Linaro Ltd.
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* Author: Al Stone <al.stone@linaro.org>
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* Author: Graeme Gregory <graeme.gregory@linaro.org>
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* Author: Hanjun Guo <hanjun.guo@linaro.org>
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*/
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#ifndef _ASM_ACPI_H
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#define _ASM_ACPI_H
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#include <linux/efi.h>
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#include <linux/memblock.h>
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#include <linux/psci.h>
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#include <linux/stddef.h>
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#include <asm/cputype.h>
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#include <asm/io.h>
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#include <asm/ptrace.h>
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#include <asm/smp_plat.h>
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#include <asm/tlbflush.h>
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/* Macros for consistency checks of the GICC subtable of MADT */
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/*
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* MADT GICC minimum length refers to the MADT GICC structure table length as
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* defined in the earliest ACPI version supported on arm64, ie ACPI 5.1.
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*
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* The efficiency_class member was added to the
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* struct acpi_madt_generic_interrupt to represent the MADT GICC structure
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* "Processor Power Efficiency Class" field, added in ACPI 6.0 whose offset
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* is therefore used to delimit the MADT GICC structure minimum length
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* appropriately.
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*/
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#define ACPI_MADT_GICC_MIN_LENGTH offsetof( \
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struct acpi_madt_generic_interrupt, efficiency_class)
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#define BAD_MADT_GICC_ENTRY(entry, end) \
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(!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \
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(unsigned long)(entry) + (entry)->header.length > (end))
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#define ACPI_MADT_GICC_SPE (offsetof(struct acpi_madt_generic_interrupt, \
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spe_interrupt) + sizeof(u16))
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/* Basic configuration for ACPI */
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#ifdef CONFIG_ACPI
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pgprot_t __acpi_get_mem_attribute(phys_addr_t addr);
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/* ACPI table mapping after acpi_permanent_mmap is set */
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void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size);
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#define acpi_os_ioremap acpi_os_ioremap
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typedef u64 phys_cpuid_t;
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#define PHYS_CPUID_INVALID INVALID_HWID
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#define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */
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extern int acpi_disabled;
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extern int acpi_noirq;
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extern int acpi_pci_disabled;
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static inline void disable_acpi(void)
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{
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acpi_disabled = 1;
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acpi_pci_disabled = 1;
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acpi_noirq = 1;
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}
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static inline void enable_acpi(void)
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{
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acpi_disabled = 0;
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acpi_pci_disabled = 0;
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acpi_noirq = 0;
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}
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/*
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* The ACPI processor driver for ACPI core code needs this macro
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* to find out this cpu was already mapped (mapping from CPU hardware
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* ID to CPU logical ID) or not.
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*/
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#define cpu_physical_id(cpu) cpu_logical_map(cpu)
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/*
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* It's used from ACPI core in kdump to boot UP system with SMP kernel,
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* with this check the ACPI core will not override the CPU index
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* obtained from GICC with 0 and not print some error message as well.
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* Since MADT must provide at least one GICC structure for GIC
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* initialization, CPU will be always available in MADT on ARM64.
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*/
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static inline bool acpi_has_cpu_in_madt(void)
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{
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return true;
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}
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struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu);
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static inline u32 get_acpi_id_for_cpu(unsigned int cpu)
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{
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return acpi_cpu_get_madt_gicc(cpu)->uid;
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}
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static inline void arch_fix_phys_package_id(int num, u32 slot) { }
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void __init acpi_init_cpus(void);
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int apei_claim_sea(struct pt_regs *regs);
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#else
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static inline void acpi_init_cpus(void) { }
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static inline int apei_claim_sea(struct pt_regs *regs) { return -ENOENT; }
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#endif /* CONFIG_ACPI */
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#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
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bool acpi_parking_protocol_valid(int cpu);
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void __init
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acpi_set_mailbox_entry(int cpu, struct acpi_madt_generic_interrupt *processor);
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#else
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static inline bool acpi_parking_protocol_valid(int cpu) { return false; }
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static inline void
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acpi_set_mailbox_entry(int cpu, struct acpi_madt_generic_interrupt *processor)
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{}
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#endif
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static inline const char *acpi_get_enable_method(int cpu)
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{
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if (acpi_psci_present())
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return "psci";
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if (acpi_parking_protocol_valid(cpu))
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return "parking-protocol";
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return NULL;
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}
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#ifdef CONFIG_ACPI_APEI
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/*
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* acpi_disable_cmcff is used in drivers/acpi/apei/hest.c for disabling
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* IA-32 Architecture Corrected Machine Check (CMC) Firmware-First mode
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* with a kernel command line parameter "acpi=nocmcoff". But we don't
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* have this IA-32 specific feature on ARM64, this definition is only
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* for compatibility.
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*/
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#define acpi_disable_cmcff 1
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static inline pgprot_t arch_apei_get_mem_attribute(phys_addr_t addr)
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{
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return __acpi_get_mem_attribute(addr);
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}
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#endif /* CONFIG_ACPI_APEI */
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#ifdef CONFIG_ACPI_NUMA
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int arm64_acpi_numa_init(void);
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int acpi_numa_get_nid(unsigned int cpu);
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void acpi_map_cpus_to_nodes(void);
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#else
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static inline int arm64_acpi_numa_init(void) { return -ENOSYS; }
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static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; }
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static inline void acpi_map_cpus_to_nodes(void) { }
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#endif /* CONFIG_ACPI_NUMA */
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#define ACPI_TABLE_UPGRADE_MAX_PHYS MEMBLOCK_ALLOC_ACCESSIBLE
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#endif /*_ASM_ACPI_H*/
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