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![Rohan McLure](/assets/img/avatar_default.png)
Inspired by (bd75b4ef49
: Constify static attribute_group structs),
accepted by linux-next, reported:
https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20220210202805.7750-4-rikard.falkeborn@gmail.com/
Nearly all singletons of type struct attribute_group are never modified,
and so are candidates for being const. Declare them as const.
Signed-off-by: Rohan McLure <rmclure@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220307231414.86560-1-rmclure@linux.ibm.com
332 lines
9 KiB
C
332 lines
9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright 2019 Madhavan Srinivasan, IBM Corporation.
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#define pr_fmt(fmt) "generic-compat-pmu: " fmt
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#include "isa207-common.h"
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/*
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* Raw event encoding:
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*
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* 60 56 52 48 44 40 36 32
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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*
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* 28 24 20 16 12 8 4 0
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ pmc ] [ pmcxsel ]
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*/
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/*
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* Event codes defined in ISA v3.0B
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*/
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#define EVENT(_name, _code) _name = _code,
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enum {
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/* Cycles, alternate code */
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EVENT(PM_CYC_ALT, 0x100f0)
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/* One or more instructions completed in a cycle */
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EVENT(PM_CYC_INST_CMPL, 0x100f2)
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/* Floating-point instruction completed */
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EVENT(PM_FLOP_CMPL, 0x100f4)
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/* Instruction ERAT/L1-TLB miss */
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EVENT(PM_L1_ITLB_MISS, 0x100f6)
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/* All instructions completed and none available */
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EVENT(PM_NO_INST_AVAIL, 0x100f8)
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/* A load-type instruction completed (ISA v3.0+) */
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EVENT(PM_LD_CMPL, 0x100fc)
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/* Instruction completed, alternate code (ISA v3.0+) */
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EVENT(PM_INST_CMPL_ALT, 0x100fe)
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/* A store-type instruction completed */
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EVENT(PM_ST_CMPL, 0x200f0)
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/* Instruction Dispatched */
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EVENT(PM_INST_DISP, 0x200f2)
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/* Run_cycles */
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EVENT(PM_RUN_CYC, 0x200f4)
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/* Data ERAT/L1-TLB miss/reload */
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EVENT(PM_L1_DTLB_RELOAD, 0x200f6)
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/* Taken branch completed */
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EVENT(PM_BR_TAKEN_CMPL, 0x200fa)
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/* Demand iCache Miss */
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EVENT(PM_L1_ICACHE_MISS, 0x200fc)
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/* L1 Dcache reload from memory */
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EVENT(PM_L1_RELOAD_FROM_MEM, 0x200fe)
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/* L1 Dcache store miss */
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EVENT(PM_ST_MISS_L1, 0x300f0)
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/* Alternate code for PM_INST_DISP */
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EVENT(PM_INST_DISP_ALT, 0x300f2)
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/* Branch direction or target mispredicted */
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EVENT(PM_BR_MISPREDICT, 0x300f6)
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/* Data TLB miss/reload */
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EVENT(PM_DTLB_MISS, 0x300fc)
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/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
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EVENT(PM_DATA_FROM_L3MISS, 0x300fe)
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/* L1 Dcache load miss */
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EVENT(PM_LD_MISS_L1, 0x400f0)
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/* Cycle when instruction(s) dispatched */
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EVENT(PM_CYC_INST_DISP, 0x400f2)
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/* Branch or branch target mispredicted */
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EVENT(PM_BR_MPRED_CMPL, 0x400f6)
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/* Instructions completed with run latch set */
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EVENT(PM_RUN_INST_CMPL, 0x400fa)
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/* Instruction TLB miss/reload */
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EVENT(PM_ITLB_MISS, 0x400fc)
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/* Load data not cached */
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EVENT(PM_LD_NOT_CACHED, 0x400fe)
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/* Instructions */
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EVENT(PM_INST_CMPL, 0x500fa)
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/* Cycles */
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EVENT(PM_CYC, 0x600f4)
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};
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#undef EVENT
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/* Table of alternatives, sorted in increasing order of column 0 */
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/* Note that in each row, column 0 must be the smallest */
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static const unsigned int generic_event_alternatives[][MAX_ALT] = {
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{ PM_CYC_ALT, PM_CYC },
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{ PM_INST_CMPL_ALT, PM_INST_CMPL },
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{ PM_INST_DISP, PM_INST_DISP_ALT },
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};
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static int generic_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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{
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int num_alt = 0;
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num_alt = isa207_get_alternatives(event, alt,
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ARRAY_SIZE(generic_event_alternatives), flags,
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generic_event_alternatives);
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return num_alt;
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}
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GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
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GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
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GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_NO_INST_AVAIL);
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GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
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GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
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CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
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CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
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CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
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CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
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CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
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CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
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CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
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static struct attribute *generic_compat_events_attr[] = {
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GENERIC_EVENT_PTR(PM_CYC),
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GENERIC_EVENT_PTR(PM_INST_CMPL),
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GENERIC_EVENT_PTR(PM_NO_INST_AVAIL),
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GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
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GENERIC_EVENT_PTR(PM_LD_MISS_L1),
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CACHE_EVENT_PTR(PM_LD_MISS_L1),
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CACHE_EVENT_PTR(PM_ST_MISS_L1),
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CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
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CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
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CACHE_EVENT_PTR(PM_DTLB_MISS),
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CACHE_EVENT_PTR(PM_ITLB_MISS),
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NULL
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};
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static const struct attribute_group generic_compat_pmu_events_group = {
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.name = "events",
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.attrs = generic_compat_events_attr,
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};
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PMU_FORMAT_ATTR(event, "config:0-19");
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PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
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PMU_FORMAT_ATTR(pmc, "config:16-19");
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static struct attribute *generic_compat_pmu_format_attr[] = {
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&format_attr_event.attr,
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&format_attr_pmcxsel.attr,
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&format_attr_pmc.attr,
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NULL,
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};
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static const struct attribute_group generic_compat_pmu_format_group = {
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.name = "format",
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.attrs = generic_compat_pmu_format_attr,
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};
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static const struct attribute_group *generic_compat_pmu_attr_groups[] = {
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&generic_compat_pmu_format_group,
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&generic_compat_pmu_events_group,
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NULL,
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};
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static int compat_generic_events[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
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[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_NO_INST_AVAIL,
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[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
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[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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*/
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static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_LD_MISS_L1,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_ST_MISS_L1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(L1I) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(LL) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_DTLB_MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_ITLB_MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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};
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#undef C
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/*
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* We set MMCR0[CC5-6RUN] so we can use counters 5 and 6 for
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* PM_INST_CMPL and PM_CYC.
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*/
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static int generic_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], struct mmcr_regs *mmcr,
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struct perf_event *pevents[], u32 flags)
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{
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int ret;
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ret = isa207_compute_mmcr(event, n_ev, hwc, mmcr, pevents, flags);
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if (!ret)
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mmcr->mmcr0 |= MMCR0_C56RUN;
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return ret;
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}
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static struct power_pmu generic_compat_pmu = {
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.name = "GENERIC_COMPAT",
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.n_counter = MAX_PMU_COUNTERS,
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.add_fields = ISA207_ADD_FIELDS,
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.test_adder = ISA207_TEST_ADDER,
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.compute_mmcr = generic_compute_mmcr,
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.get_constraint = isa207_get_constraint,
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.get_alternatives = generic_get_alternatives,
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.disable_pmc = isa207_disable_pmc,
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.flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
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.n_generic = ARRAY_SIZE(compat_generic_events),
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.generic_events = compat_generic_events,
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.cache_events = &generic_compat_cache_events,
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.attr_groups = generic_compat_pmu_attr_groups,
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};
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int __init init_generic_compat_pmu(void)
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{
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int rc = 0;
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/*
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* From ISA v2.07 on, PMU features are architected;
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* we require >= v3.0 because (a) that has PM_LD_CMPL and
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* PM_INST_CMPL_ALT, which v2.07 doesn't have, and
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* (b) we don't expect any non-IBM Power ISA
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* implementations that conform to v2.07 but not v3.0.
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*/
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -ENODEV;
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rc = register_power_pmu(&generic_compat_pmu);
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if (rc)
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return rc;
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/* Tell userspace that EBB is supported */
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cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
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return 0;
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}
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