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c6cc9a852f
When scheduling a group of events, there are constraint checks done to
make sure all events can go in a group. Example, one of the criteria is
that events in a group cannot use the same PMC. But platform specific
PMU supports alternative event for some of the event codes. During
perf_event_open(), if any event group doesn't match constraint check
criteria, further lookup is done to find alternative event.
By current design, the array of alternatives events in PMU code is
expected to be sorted by column 0. This is because in
find_alternative() the return criteria is based on event code
comparison. ie. "event < ev_alt[i][0])". This optimisation is there
since find_alternative() can be called multiple times. In power10 PMU
code, the alternative event array is not sorted properly and hence there
is breakage in finding alternative event.
To work with existing logic, fix the alternative event array to be
sorted by column 0 for power10-pmu.c
Results:
In case where an alternative event is not chosen when we could, events
will be multiplexed. ie, time sliced where it could actually run
concurrently.
Example, in power10 PM_INST_CMPL_ALT(0x00002) has alternative event,
PM_INST_CMPL(0x500fa). Without the fix, if a group of events with PMC1
to PMC4 is used along with PM_INST_CMPL_ALT, it will be time sliced
since all programmable PMC's are consumed already. But with the fix,
when it picks alternative event on PMC5, all events will run
concurrently.
Before:
# perf stat -e r00002,r100fc,r200fa,r300fc,r400fc
Performance counter stats for 'system wide':
328668935 r00002 (79.94%)
56501024 r100fc (79.95%)
49564238 r200fa (79.95%)
376 r300fc (80.19%)
660 r400fc (79.97%)
4.039150522 seconds time elapsed
With the fix, since alternative event is chosen to run on PMC6, events
will be run concurrently.
After:
# perf stat -e r00002,r100fc,r200fa,r300fc,r400fc
Performance counter stats for 'system wide':
23596607 r00002
4907738 r100fc
2283608 r200fa
135 r300fc
248 r400fc
1.664671390 seconds time elapsed
Fixes: a64e697cef ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220419114828.89843-2-atrajeev@linux.vnet.ibm.com
627 lines
17 KiB
C
627 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Performance counter support for POWER10 processors.
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*
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* Copyright 2020 Madhavan Srinivasan, IBM Corporation.
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* Copyright 2020 Athira Rajeev, IBM Corporation.
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*/
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#define pr_fmt(fmt) "power10-pmu: " fmt
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#include "isa207-common.h"
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/*
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* Raw event encoding for Power10:
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*
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* 60 56 52 48 44 40 36 32
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* | | [ ] [ src_match ] [ src_mask ] | [ ] [ l2l3_sel ] [ thresh_ctl ]
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* | | | | | |
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* | | *- IFM (Linux) | | thresh start/stop -*
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* | *- BHRB (Linux) | src_sel
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* *- EBB (Linux) *invert_bit
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*
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* 28 24 20 16 12 8 4 0
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] | m [ pmcxsel ]
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* | | | | | | |
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* | | | | | | *- mark
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* | | | *- L1/L2/L3 cache_sel | |*-radix_scope_qual
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* | | sdar_mode |
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* | *- sampling mode for marked events *- combine
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* |
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* *- thresh_sel
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*
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* Below uses IBM bit numbering.
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*
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* MMCR1[x:y] = unit (PMCxUNIT)
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* MMCR1[24] = pmc1combine[0]
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* MMCR1[25] = pmc1combine[1]
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* MMCR1[26] = pmc2combine[0]
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* MMCR1[27] = pmc2combine[1]
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* MMCR1[28] = pmc3combine[0]
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* MMCR1[29] = pmc3combine[1]
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* MMCR1[30] = pmc4combine[0]
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* MMCR1[31] = pmc4combine[1]
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*
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* if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
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* MMCR1[20:27] = thresh_ctl
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* else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
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* MMCR1[20:27] = thresh_ctl
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* else
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* MMCRA[48:55] = thresh_ctl (THRESH START/END)
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*
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* if thresh_sel:
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* MMCRA[45:47] = thresh_sel
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*
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* if l2l3_sel:
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* MMCR2[56:60] = l2l3_sel[0:4]
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*
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* MMCR1[16] = cache_sel[0]
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* MMCR1[17] = cache_sel[1]
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* MMCR1[18] = radix_scope_qual
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*
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* if mark:
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* MMCRA[63] = 1 (SAMPLE_ENABLE)
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* MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
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* MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
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*
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* if EBB and BHRB:
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* MMCRA[32:33] = IFM
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*
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* MMCRA[SDAR_MODE] = sdar_mode[0:1]
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*/
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/*
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* Some power10 event codes.
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*/
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#define EVENT(_name, _code) enum{_name = _code}
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#include "power10-events-list.h"
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#undef EVENT
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/* MMCRA IFM bits - POWER10 */
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#define POWER10_MMCRA_IFM1 0x0000000040000000UL
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#define POWER10_MMCRA_IFM2 0x0000000080000000UL
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#define POWER10_MMCRA_IFM3 0x00000000C0000000UL
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#define POWER10_MMCRA_BHRB_MASK 0x00000000C0000000UL
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extern u64 PERF_REG_EXTENDED_MASK;
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/* Table of alternatives, sorted by column 0 */
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static const unsigned int power10_event_alternatives[][MAX_ALT] = {
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{ PM_INST_CMPL_ALT, PM_INST_CMPL },
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{ PM_CYC_ALT, PM_CYC },
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};
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static int power10_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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{
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int num_alt = 0;
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num_alt = isa207_get_alternatives(event, alt,
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ARRAY_SIZE(power10_event_alternatives), flags,
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power10_event_alternatives);
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return num_alt;
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}
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static int power10_check_attr_config(struct perf_event *ev)
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{
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u64 val;
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u64 event = ev->attr.config;
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val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
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if (val == 0x10 || isa3XX_check_attr_config(ev))
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return -EINVAL;
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return 0;
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}
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GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
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GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
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GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL);
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GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
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GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
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GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
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GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS);
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GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
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GENERIC_EVENT_ATTR(branch-instructions, PM_BR_FIN);
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GENERIC_EVENT_ATTR(branch-misses, PM_MPRED_BR_FIN);
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GENERIC_EVENT_ATTR(cache-misses, PM_LD_DEMAND_MISS_L1_FIN);
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CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
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CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
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CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS);
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CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
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CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
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CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
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CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
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CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
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CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
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CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PF_MISS_L3);
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CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
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CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
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CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
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CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
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CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
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CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
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static struct attribute *power10_events_attr_dd1[] = {
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GENERIC_EVENT_PTR(PM_CYC),
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GENERIC_EVENT_PTR(PM_INST_CMPL),
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GENERIC_EVENT_PTR(PM_BR_CMPL),
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GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
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GENERIC_EVENT_PTR(PM_LD_REF_L1),
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GENERIC_EVENT_PTR(PM_LD_MISS_L1),
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GENERIC_EVENT_PTR(MEM_LOADS),
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GENERIC_EVENT_PTR(MEM_STORES),
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CACHE_EVENT_PTR(PM_LD_MISS_L1),
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CACHE_EVENT_PTR(PM_LD_REF_L1),
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CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS),
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CACHE_EVENT_PTR(PM_ST_MISS_L1),
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CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
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CACHE_EVENT_PTR(PM_INST_FROM_L1),
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CACHE_EVENT_PTR(PM_IC_PREF_REQ),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3),
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CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
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CACHE_EVENT_PTR(PM_BR_CMPL),
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CACHE_EVENT_PTR(PM_DTLB_MISS),
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CACHE_EVENT_PTR(PM_ITLB_MISS),
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NULL
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};
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static struct attribute *power10_events_attr[] = {
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GENERIC_EVENT_PTR(PM_CYC),
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GENERIC_EVENT_PTR(PM_INST_CMPL),
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GENERIC_EVENT_PTR(PM_BR_FIN),
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GENERIC_EVENT_PTR(PM_MPRED_BR_FIN),
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GENERIC_EVENT_PTR(PM_LD_REF_L1),
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GENERIC_EVENT_PTR(PM_LD_DEMAND_MISS_L1_FIN),
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GENERIC_EVENT_PTR(MEM_LOADS),
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GENERIC_EVENT_PTR(MEM_STORES),
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CACHE_EVENT_PTR(PM_LD_MISS_L1),
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CACHE_EVENT_PTR(PM_LD_REF_L1),
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CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS),
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CACHE_EVENT_PTR(PM_ST_MISS_L1),
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CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
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CACHE_EVENT_PTR(PM_INST_FROM_L1),
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CACHE_EVENT_PTR(PM_IC_PREF_REQ),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3),
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CACHE_EVENT_PTR(PM_L3_PF_MISS_L3),
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CACHE_EVENT_PTR(PM_L2_ST_MISS),
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CACHE_EVENT_PTR(PM_L2_ST),
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CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
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CACHE_EVENT_PTR(PM_BR_CMPL),
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CACHE_EVENT_PTR(PM_DTLB_MISS),
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CACHE_EVENT_PTR(PM_ITLB_MISS),
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NULL
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};
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static const struct attribute_group power10_pmu_events_group_dd1 = {
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.name = "events",
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.attrs = power10_events_attr_dd1,
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};
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static const struct attribute_group power10_pmu_events_group = {
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.name = "events",
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.attrs = power10_events_attr,
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};
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PMU_FORMAT_ATTR(event, "config:0-59");
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PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
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PMU_FORMAT_ATTR(mark, "config:8");
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PMU_FORMAT_ATTR(combine, "config:10-11");
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PMU_FORMAT_ATTR(unit, "config:12-15");
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PMU_FORMAT_ATTR(pmc, "config:16-19");
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PMU_FORMAT_ATTR(cache_sel, "config:20-21");
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PMU_FORMAT_ATTR(sdar_mode, "config:22-23");
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PMU_FORMAT_ATTR(sample_mode, "config:24-28");
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PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
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PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
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PMU_FORMAT_ATTR(thresh_start, "config:36-39");
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PMU_FORMAT_ATTR(l2l3_sel, "config:40-44");
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PMU_FORMAT_ATTR(src_sel, "config:45-46");
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PMU_FORMAT_ATTR(invert_bit, "config:47");
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PMU_FORMAT_ATTR(src_mask, "config:48-53");
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PMU_FORMAT_ATTR(src_match, "config:54-59");
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PMU_FORMAT_ATTR(radix_scope, "config:9");
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PMU_FORMAT_ATTR(thresh_cmp, "config1:0-17");
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static struct attribute *power10_pmu_format_attr[] = {
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&format_attr_event.attr,
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&format_attr_pmcxsel.attr,
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&format_attr_mark.attr,
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&format_attr_combine.attr,
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&format_attr_unit.attr,
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&format_attr_pmc.attr,
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&format_attr_cache_sel.attr,
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&format_attr_sdar_mode.attr,
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&format_attr_sample_mode.attr,
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&format_attr_thresh_sel.attr,
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&format_attr_thresh_stop.attr,
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&format_attr_thresh_start.attr,
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&format_attr_l2l3_sel.attr,
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&format_attr_src_sel.attr,
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&format_attr_invert_bit.attr,
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&format_attr_src_mask.attr,
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&format_attr_src_match.attr,
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&format_attr_radix_scope.attr,
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&format_attr_thresh_cmp.attr,
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NULL,
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};
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static const struct attribute_group power10_pmu_format_group = {
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.name = "format",
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.attrs = power10_pmu_format_attr,
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};
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static const struct attribute_group *power10_pmu_attr_groups_dd1[] = {
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&power10_pmu_format_group,
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&power10_pmu_events_group_dd1,
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NULL,
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};
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static const struct attribute_group *power10_pmu_attr_groups[] = {
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&power10_pmu_format_group,
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&power10_pmu_events_group,
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NULL,
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};
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static int power10_generic_events_dd1[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
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[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL,
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[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
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[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
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[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
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};
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static int power10_generic_events[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
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[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_FIN,
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[PERF_COUNT_HW_BRANCH_MISSES] = PM_MPRED_BR_FIN,
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[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
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[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_DEMAND_MISS_L1_FIN,
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};
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static u64 power10_bhrb_filter_map(u64 branch_sample_type)
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{
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u64 pmu_bhrb_filter = 0;
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/* BHRB and regular PMU events share the same privilege state
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* filter configuration. BHRB is always recorded along with a
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* regular PMU event. As the privilege state filter is handled
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* in the basic PMC configuration of the accompanying regular
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* PMU event, we ignore any separate BHRB specific request.
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*/
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/* No branch filter requested */
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if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
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return pmu_bhrb_filter;
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/* Invalid branch filter options - HW does not support */
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if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
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return -1;
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if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) {
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pmu_bhrb_filter |= POWER10_MMCRA_IFM2;
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return pmu_bhrb_filter;
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}
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if (branch_sample_type & PERF_SAMPLE_BRANCH_COND) {
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pmu_bhrb_filter |= POWER10_MMCRA_IFM3;
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return pmu_bhrb_filter;
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}
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if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
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return -1;
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if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
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pmu_bhrb_filter |= POWER10_MMCRA_IFM1;
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return pmu_bhrb_filter;
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}
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/* Every thing else is unsupported */
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return -1;
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}
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static void power10_config_bhrb(u64 pmu_bhrb_filter)
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{
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pmu_bhrb_filter &= POWER10_MMCRA_BHRB_MASK;
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/* Enable BHRB filter in PMU */
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mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
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}
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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*/
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static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PM_LD_REF_L1,
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[C(RESULT_MISS)] = PM_LD_MISS_L1,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = 0,
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[C(RESULT_MISS)] = PM_ST_MISS_L1,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
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[C(RESULT_MISS)] = 0,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PM_INST_FROM_L1,
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[C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
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[C(RESULT_MISS)] = -1,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
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[C(RESULT_MISS)] = 0,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
|
|
[C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = 0,
|
|
},
|
|
},
|
|
[C(DTLB)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = 0,
|
|
[C(RESULT_MISS)] = PM_DTLB_MISS,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
},
|
|
[C(ITLB)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = 0,
|
|
[C(RESULT_MISS)] = PM_ITLB_MISS,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
},
|
|
[C(BPU)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = PM_BR_CMPL,
|
|
[C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
},
|
|
[C(NODE)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
},
|
|
};
|
|
|
|
static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
|
|
[C(L1D)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = PM_LD_REF_L1,
|
|
[C(RESULT_MISS)] = PM_LD_MISS_L1,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = 0,
|
|
[C(RESULT_MISS)] = PM_ST_MISS_L1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
|
|
[C(RESULT_MISS)] = 0,
|
|
},
|
|
},
|
|
[C(L1I)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = PM_INST_FROM_L1,
|
|
[C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
|
|
[C(RESULT_MISS)] = 0,
|
|
},
|
|
},
|
|
[C(LL)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
|
|
[C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = PM_L2_ST,
|
|
[C(RESULT_MISS)] = PM_L2_ST_MISS,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = PM_L3_PF_MISS_L3,
|
|
[C(RESULT_MISS)] = 0,
|
|
},
|
|
},
|
|
[C(DTLB)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = 0,
|
|
[C(RESULT_MISS)] = PM_DTLB_MISS,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
},
|
|
[C(ITLB)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = 0,
|
|
[C(RESULT_MISS)] = PM_ITLB_MISS,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
},
|
|
[C(BPU)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = PM_BR_CMPL,
|
|
[C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
},
|
|
[C(NODE)] = {
|
|
[C(OP_READ)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_WRITE)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
[C(OP_PREFETCH)] = {
|
|
[C(RESULT_ACCESS)] = -1,
|
|
[C(RESULT_MISS)] = -1,
|
|
},
|
|
},
|
|
};
|
|
|
|
#undef C
|
|
|
|
/*
|
|
* Set the MMCR0[CC56RUN] bit to enable counting for
|
|
* PMC5 and PMC6 regardless of the state of CTRL[RUN],
|
|
* so that we can use counters 5 and 6 as PM_INST_CMPL and
|
|
* PM_CYC.
|
|
*/
|
|
static int power10_compute_mmcr(u64 event[], int n_ev,
|
|
unsigned int hwc[], struct mmcr_regs *mmcr,
|
|
struct perf_event *pevents[], u32 flags)
|
|
{
|
|
int ret;
|
|
|
|
ret = isa207_compute_mmcr(event, n_ev, hwc, mmcr, pevents, flags);
|
|
if (!ret)
|
|
mmcr->mmcr0 |= MMCR0_C56RUN;
|
|
return ret;
|
|
}
|
|
|
|
static struct power_pmu power10_pmu = {
|
|
.name = "POWER10",
|
|
.n_counter = MAX_PMU_COUNTERS,
|
|
.add_fields = ISA207_ADD_FIELDS,
|
|
.test_adder = ISA207_TEST_ADDER,
|
|
.group_constraint_mask = CNST_CACHE_PMC4_MASK,
|
|
.group_constraint_val = CNST_CACHE_PMC4_VAL,
|
|
.compute_mmcr = power10_compute_mmcr,
|
|
.config_bhrb = power10_config_bhrb,
|
|
.bhrb_filter_map = power10_bhrb_filter_map,
|
|
.get_constraint = isa207_get_constraint,
|
|
.get_alternatives = power10_get_alternatives,
|
|
.get_mem_data_src = isa207_get_mem_data_src,
|
|
.get_mem_weight = isa207_get_mem_weight,
|
|
.disable_pmc = isa207_disable_pmc,
|
|
.flags = PPMU_HAS_SIER | PPMU_ARCH_207S |
|
|
PPMU_ARCH_31 | PPMU_HAS_ATTR_CONFIG1,
|
|
.n_generic = ARRAY_SIZE(power10_generic_events),
|
|
.generic_events = power10_generic_events,
|
|
.cache_events = &power10_cache_events,
|
|
.attr_groups = power10_pmu_attr_groups,
|
|
.bhrb_nr = 32,
|
|
.capabilities = PERF_PMU_CAP_EXTENDED_REGS,
|
|
.check_attr_config = power10_check_attr_config,
|
|
};
|
|
|
|
int __init init_power10_pmu(void)
|
|
{
|
|
unsigned int pvr;
|
|
int rc;
|
|
|
|
/* Comes from cpu_specs[] */
|
|
if (!cur_cpu_spec->oprofile_cpu_type ||
|
|
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10"))
|
|
return -ENODEV;
|
|
|
|
pvr = mfspr(SPRN_PVR);
|
|
/* Add the ppmu flag for power10 DD1 */
|
|
if ((PVR_CFG(pvr) == 1))
|
|
power10_pmu.flags |= PPMU_P10_DD1;
|
|
|
|
/* Set the PERF_REG_EXTENDED_MASK here */
|
|
PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31;
|
|
|
|
if ((PVR_CFG(pvr) == 1)) {
|
|
power10_pmu.generic_events = power10_generic_events_dd1;
|
|
power10_pmu.attr_groups = power10_pmu_attr_groups_dd1;
|
|
power10_pmu.cache_events = &power10_cache_events_dd1;
|
|
}
|
|
|
|
rc = register_power_pmu(&power10_pmu);
|
|
if (rc)
|
|
return rc;
|
|
|
|
/* Tell userspace that EBB is supported */
|
|
cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
|
|
|
|
return 0;
|
|
}
|