81 lines
1.9 KiB
Plaintext
81 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/Five SoC
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
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#include <arm64/renesas/r9a07g043.dtsi>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <12000000>;
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cpu0: cpu@0 {
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compatible = "andestech,ax45mp", "riscv";
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device_type = "cpu";
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#cooling-cells = <2>;
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reg = <0x0>;
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status = "okay";
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"zicntr", "zicsr", "zifencei",
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"zihpm", "xandespmu";
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mmu-type = "riscv,sv39";
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i-cache-size = <0x8000>;
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i-cache-line-size = <0x40>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <0x40>;
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next-level-cache = <&l2cache>;
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clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
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operating-points-v2 = <&cluster0_opp>;
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "andestech,cpu-intc", "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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};
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&pinctrl {
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gpio-ranges = <&pinctrl 0 0 232>;
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};
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&soc {
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dma-noncoherent;
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interrupt-parent = <&plic>;
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plic: interrupt-controller@12c00000 {
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compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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riscv,ndev = <511>;
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interrupt-controller;
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reg = <0x0 0x12c00000 0 0x400000>;
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clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
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interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
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};
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l2cache: cache-controller@13400000 {
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compatible = "andestech,ax45mp-cache", "cache";
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reg = <0x0 0x13400000 0x0 0x100000>;
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interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
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cache-size = <0x40000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-unified;
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cache-level = <2>;
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};
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};
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