377 lines
9.5 KiB
C
377 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_BITOPS_H
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#define _ASM_RISCV_BITOPS_H
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#ifndef _LINUX_BITOPS_H
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#error "Only <linux/bitops.h> can be included directly"
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#endif /* _LINUX_BITOPS_H */
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#include <linux/compiler.h>
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#include <linux/irqflags.h>
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#include <asm/barrier.h>
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#include <asm/bitsperlong.h>
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#if !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE)
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#include <asm-generic/bitops/__ffs.h>
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#include <asm-generic/bitops/__fls.h>
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#include <asm-generic/bitops/ffs.h>
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#include <asm-generic/bitops/fls.h>
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#else
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#define __HAVE_ARCH___FFS
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#define __HAVE_ARCH___FLS
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#define __HAVE_ARCH_FFS
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#define __HAVE_ARCH_FLS
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#include <asm-generic/bitops/__ffs.h>
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#include <asm-generic/bitops/__fls.h>
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#include <asm-generic/bitops/ffs.h>
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#include <asm-generic/bitops/fls.h>
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#include <asm/alternative-macros.h>
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#include <asm/hwcap.h>
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#if (BITS_PER_LONG == 64)
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#define CTZW "ctzw "
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#define CLZW "clzw "
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#elif (BITS_PER_LONG == 32)
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#define CTZW "ctz "
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#define CLZW "clz "
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#else
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#error "Unexpected BITS_PER_LONG"
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#endif
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static __always_inline unsigned long variable__ffs(unsigned long word)
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{
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asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
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RISCV_ISA_EXT_ZBB, 1)
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: : : : legacy);
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asm volatile (".option push\n"
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".option arch,+zbb\n"
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"ctz %0, %1\n"
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".option pop\n"
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: "=r" (word) : "r" (word) :);
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return word;
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legacy:
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return generic___ffs(word);
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}
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/**
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* __ffs - find first set bit in a long word
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* @word: The word to search
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*
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* Undefined if no set bit exists, so code should check against 0 first.
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*/
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#define __ffs(word) \
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(__builtin_constant_p(word) ? \
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(unsigned long)__builtin_ctzl(word) : \
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variable__ffs(word))
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static __always_inline unsigned long variable__fls(unsigned long word)
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{
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asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
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RISCV_ISA_EXT_ZBB, 1)
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: : : : legacy);
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asm volatile (".option push\n"
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".option arch,+zbb\n"
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"clz %0, %1\n"
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".option pop\n"
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: "=r" (word) : "r" (word) :);
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return BITS_PER_LONG - 1 - word;
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legacy:
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return generic___fls(word);
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}
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/**
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* __fls - find last set bit in a long word
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* @word: the word to search
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*
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* Undefined if no set bit exists, so code should check against 0 first.
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*/
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#define __fls(word) \
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(__builtin_constant_p(word) ? \
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(unsigned long)(BITS_PER_LONG - 1 - __builtin_clzl(word)) : \
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variable__fls(word))
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static __always_inline int variable_ffs(int x)
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{
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asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
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RISCV_ISA_EXT_ZBB, 1)
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: : : : legacy);
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if (!x)
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return 0;
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asm volatile (".option push\n"
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".option arch,+zbb\n"
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CTZW "%0, %1\n"
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".option pop\n"
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: "=r" (x) : "r" (x) :);
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return x + 1;
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legacy:
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return generic_ffs(x);
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}
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/**
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* ffs - find first set bit in a word
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* @x: the word to search
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*
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* This is defined the same way as the libc and compiler builtin ffs routines.
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*
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* ffs(value) returns 0 if value is 0 or the position of the first set bit if
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* value is nonzero. The first (least significant) bit is at position 1.
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*/
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#define ffs(x) (__builtin_constant_p(x) ? __builtin_ffs(x) : variable_ffs(x))
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static __always_inline int variable_fls(unsigned int x)
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{
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asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
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RISCV_ISA_EXT_ZBB, 1)
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: : : : legacy);
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if (!x)
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return 0;
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asm volatile (".option push\n"
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".option arch,+zbb\n"
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CLZW "%0, %1\n"
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".option pop\n"
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: "=r" (x) : "r" (x) :);
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return 32 - x;
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legacy:
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return generic_fls(x);
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}
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/**
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* fls - find last set bit in a word
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* @x: the word to search
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*
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* This is defined in a similar way as ffs, but returns the position of the most
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* significant set bit.
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*
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* fls(value) returns 0 if value is 0 or the position of the last set bit if
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* value is nonzero. The last (most significant) bit is at position 32.
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*/
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#define fls(x) \
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({ \
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typeof(x) x_ = (x); \
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__builtin_constant_p(x_) ? \
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(int)((x_ != 0) ? (32 - __builtin_clz(x_)) : 0) \
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: \
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variable_fls(x_); \
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})
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#endif /* !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE) */
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#include <asm-generic/bitops/ffz.h>
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm/arch_hweight.h>
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#include <asm-generic/bitops/const_hweight.h>
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#if (BITS_PER_LONG == 64)
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#define __AMO(op) "amo" #op ".d"
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#elif (BITS_PER_LONG == 32)
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#define __AMO(op) "amo" #op ".w"
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#else
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#error "Unexpected BITS_PER_LONG"
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#endif
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#define __test_and_op_bit_ord(op, mod, nr, addr, ord) \
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({ \
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unsigned long __res, __mask; \
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__mask = BIT_MASK(nr); \
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__asm__ __volatile__ ( \
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__AMO(op) #ord " %0, %2, %1" \
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: "=r" (__res), "+A" (addr[BIT_WORD(nr)]) \
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: "r" (mod(__mask)) \
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: "memory"); \
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((__res & __mask) != 0); \
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})
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#define __op_bit_ord(op, mod, nr, addr, ord) \
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__asm__ __volatile__ ( \
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__AMO(op) #ord " zero, %1, %0" \
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: "+A" (addr[BIT_WORD(nr)]) \
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: "r" (mod(BIT_MASK(nr))) \
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: "memory");
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#define __test_and_op_bit(op, mod, nr, addr) \
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__test_and_op_bit_ord(op, mod, nr, addr, .aqrl)
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#define __op_bit(op, mod, nr, addr) \
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__op_bit_ord(op, mod, nr, addr, )
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/* Bitmask modifiers */
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#define __NOP(x) (x)
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#define __NOT(x) (~(x))
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation may be reordered on other architectures than x86.
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*/
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static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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return __test_and_op_bit(or, __NOP, nr, addr);
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation can be reordered on other architectures other than x86.
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*/
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static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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return __test_and_op_bit(and, __NOT, nr, addr);
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}
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/**
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
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{
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return __test_and_op_bit(xor, __NOP, nr, addr);
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}
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Note: there are no guarantees that this function will not be reordered
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* on non x86 architectures, so if you are writing portable code,
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* make sure not to rely on its reordering guarantees.
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*
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void set_bit(int nr, volatile unsigned long *addr)
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{
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__op_bit(or, __NOP, nr, addr);
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* Note: there are no guarantees that this function will not be reordered
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* on non x86 architectures, so if you are writing portable code,
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* make sure not to rely on its reordering guarantees.
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*/
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static inline void clear_bit(int nr, volatile unsigned long *addr)
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{
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__op_bit(and, __NOT, nr, addr);
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() may be reordered on other architectures than x86.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void change_bit(int nr, volatile unsigned long *addr)
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{
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__op_bit(xor, __NOP, nr, addr);
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}
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/**
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* test_and_set_bit_lock - Set a bit and return its old value, for lock
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and provides acquire barrier semantics.
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* It can be used to implement bit locks.
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*/
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static inline int test_and_set_bit_lock(
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unsigned long nr, volatile unsigned long *addr)
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{
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return __test_and_op_bit_ord(or, __NOP, nr, addr, .aq);
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}
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/**
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* clear_bit_unlock - Clear a bit in memory, for unlock
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This operation is atomic and provides release barrier semantics.
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*/
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static inline void clear_bit_unlock(
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unsigned long nr, volatile unsigned long *addr)
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{
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__op_bit_ord(and, __NOT, nr, addr, .rl);
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}
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/**
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* __clear_bit_unlock - Clear a bit in memory, for unlock
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This operation is like clear_bit_unlock, however it is not atomic.
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* It does provide release barrier semantics so it can be used to unlock
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* a bit lock, however it would only be used if no other CPU can modify
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* any bits in the memory until the lock is released (a good example is
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* if the bit lock itself protects access to the other bits in the word).
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*
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* On RISC-V systems there seems to be no benefit to taking advantage of the
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* non-atomic property here: it's a lot more instructions and we still have to
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* provide release semantics anyway.
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*/
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static inline void __clear_bit_unlock(
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unsigned long nr, volatile unsigned long *addr)
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{
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clear_bit_unlock(nr, addr);
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}
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static inline bool xor_unlock_is_negative_byte(unsigned long mask,
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volatile unsigned long *addr)
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{
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unsigned long res;
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__asm__ __volatile__ (
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__AMO(xor) ".rl %0, %2, %1"
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: "=r" (res), "+A" (*addr)
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: "r" (__NOP(mask))
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: "memory");
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return (res & BIT(7)) != 0;
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}
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#undef __test_and_op_bit
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#undef __op_bit
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#undef __NOP
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#undef __NOT
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#undef __AMO
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#include <asm-generic/bitops/non-atomic.h>
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/ext2-atomic.h>
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#endif /* _ASM_RISCV_BITOPS_H */
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