51 lines
1.7 KiB
C
51 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _ASM_RISCV_MEMBARRIER_H
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#define _ASM_RISCV_MEMBARRIER_H
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static inline void membarrier_arch_switch_mm(struct mm_struct *prev,
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struct mm_struct *next,
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struct task_struct *tsk)
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{
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/*
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* Only need the full barrier when switching between processes.
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* Barrier when switching from kernel to userspace is not
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* required here, given that it is implied by mmdrop(). Barrier
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* when switching from userspace to kernel is not needed after
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* store to rq->curr.
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*/
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if (IS_ENABLED(CONFIG_SMP) &&
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likely(!(atomic_read(&next->membarrier_state) &
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(MEMBARRIER_STATE_PRIVATE_EXPEDITED |
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MEMBARRIER_STATE_GLOBAL_EXPEDITED)) || !prev))
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return;
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/*
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* The membarrier system call requires a full memory barrier
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* after storing to rq->curr, before going back to user-space.
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*
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* This barrier is also needed for the SYNC_CORE command when
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* switching between processes; in particular, on a transition
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* from a thread belonging to another mm to a thread belonging
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* to the mm for which a membarrier SYNC_CORE is done on CPU0:
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*
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* - [CPU0] sets all bits in the mm icache_stale_mask (in
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* prepare_sync_core_cmd());
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*
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* - [CPU1] stores to rq->curr (by the scheduler);
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*
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* - [CPU0] loads rq->curr within membarrier and observes
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* cpu_rq(1)->curr->mm != mm, so the IPI is skipped on
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* CPU1; this means membarrier relies on switch_mm() to
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* issue the sync-core;
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*
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* - [CPU1] switch_mm() loads icache_stale_mask; if the bit
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* is zero, switch_mm() may incorrectly skip the sync-core.
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*
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* Matches a full barrier in the proximity of the membarrier
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* system call entry.
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*/
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smp_mb();
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}
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#endif /* _ASM_RISCV_MEMBARRIER_H */
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