30 lines
689 B
C
30 lines
689 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_SYNC_CORE_H
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#define _ASM_RISCV_SYNC_CORE_H
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/*
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* RISC-V implements return to user-space through an xRET instruction,
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* which is not core serializing.
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*/
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static inline void sync_core_before_usermode(void)
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{
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asm volatile ("fence.i" ::: "memory");
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}
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#ifdef CONFIG_SMP
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/*
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* Ensure the next switch_mm() on every CPU issues a core serializing
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* instruction for the given @mm.
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*/
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static inline void prepare_sync_core_cmd(struct mm_struct *mm)
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{
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cpumask_setall(&mm->context.icache_stale_mask);
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}
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#else
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static inline void prepare_sync_core_cmd(struct mm_struct *mm)
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{
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}
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#endif /* CONFIG_SMP */
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#endif /* _ASM_RISCV_SYNC_CORE_H */
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