362 lines
9.3 KiB
ArmAsm
362 lines
9.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/asm.h>
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#include <asm/csr.h>
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#include <asm/scs.h>
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#include <asm/unistd.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/errata_list.h>
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#include <linux/sizes.h>
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.section .irqentry.text, "ax"
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SYM_CODE_START(handle_exception)
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/*
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* If coming from userspace, preserve the user thread pointer and load
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* the kernel thread pointer. If we came from the kernel, the scratch
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* register will contain 0, and we should continue on the current TP.
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*/
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csrrw tp, CSR_SCRATCH, tp
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bnez tp, .Lsave_context
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.Lrestore_kernel_tpsp:
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csrr tp, CSR_SCRATCH
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REG_S sp, TASK_TI_KERNEL_SP(tp)
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#ifdef CONFIG_VMAP_STACK
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addi sp, sp, -(PT_SIZE_ON_STACK)
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srli sp, sp, THREAD_SHIFT
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andi sp, sp, 0x1
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bnez sp, handle_kernel_stack_overflow
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REG_L sp, TASK_TI_KERNEL_SP(tp)
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#endif
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.Lsave_context:
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REG_S sp, TASK_TI_USER_SP(tp)
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REG_L sp, TASK_TI_KERNEL_SP(tp)
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addi sp, sp, -(PT_SIZE_ON_STACK)
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REG_S x1, PT_RA(sp)
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REG_S x3, PT_GP(sp)
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REG_S x5, PT_T0(sp)
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save_from_x6_to_x31
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/*
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* Disable user-mode memory access as it should only be set in the
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* actual user copy routines.
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*
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* Disable the FPU/Vector to detect illegal usage of floating point
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* or vector in kernel space.
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*/
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li t0, SR_SUM | SR_FS_VS
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REG_L s0, TASK_TI_USER_SP(tp)
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csrrc s1, CSR_STATUS, t0
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csrr s2, CSR_EPC
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csrr s3, CSR_TVAL
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csrr s4, CSR_CAUSE
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csrr s5, CSR_SCRATCH
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REG_S s0, PT_SP(sp)
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REG_S s1, PT_STATUS(sp)
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REG_S s2, PT_EPC(sp)
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REG_S s3, PT_BADADDR(sp)
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REG_S s4, PT_CAUSE(sp)
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REG_S s5, PT_TP(sp)
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/*
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* Set the scratch register to 0, so that if a recursive exception
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* occurs, the exception vector knows it came from the kernel
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*/
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csrw CSR_SCRATCH, x0
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/* Load the global pointer */
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load_global_pointer
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/* Load the kernel shadow call stack pointer if coming from userspace */
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scs_load_current_if_task_changed s5
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#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE
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move a0, sp
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call riscv_v_context_nesting_start
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#endif
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move a0, sp /* pt_regs */
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la ra, ret_from_exception
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/*
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* MSB of cause differentiates between
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* interrupts and exceptions
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*/
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bge s4, zero, 1f
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/* Handle interrupts */
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tail do_irq
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1:
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/* Handle other exceptions */
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slli t0, s4, RISCV_LGPTR
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la t1, excp_vect_table
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la t2, excp_vect_table_end
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add t0, t1, t0
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/* Check if exception code lies within bounds */
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bgeu t0, t2, 1f
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REG_L t0, 0(t0)
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jr t0
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1:
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tail do_trap_unknown
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SYM_CODE_END(handle_exception)
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ASM_NOKPROBE(handle_exception)
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/*
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* The ret_from_exception must be called with interrupt disabled. Here is the
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* caller list:
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* - handle_exception
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* - ret_from_fork
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*/
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SYM_CODE_START_NOALIGN(ret_from_exception)
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REG_L s0, PT_STATUS(sp)
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#ifdef CONFIG_RISCV_M_MODE
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/* the MPP value is too large to be used as an immediate arg for addi */
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li t0, SR_MPP
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and s0, s0, t0
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#else
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andi s0, s0, SR_SPP
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#endif
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bnez s0, 1f
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/* Save unwound kernel stack pointer in thread_info */
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addi s0, sp, PT_SIZE_ON_STACK
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REG_S s0, TASK_TI_KERNEL_SP(tp)
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/* Save the kernel shadow call stack pointer */
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scs_save_current
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/*
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* Save TP into the scratch register , so we can find the kernel data
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* structures again.
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*/
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csrw CSR_SCRATCH, tp
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1:
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#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE
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move a0, sp
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call riscv_v_context_nesting_end
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#endif
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REG_L a0, PT_STATUS(sp)
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/*
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* The current load reservation is effectively part of the processor's
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* state, in the sense that load reservations cannot be shared between
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* different hart contexts. We can't actually save and restore a load
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* reservation, so instead here we clear any existing reservation --
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* it's always legal for implementations to clear load reservations at
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* any point (as long as the forward progress guarantee is kept, but
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* we'll ignore that here).
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*
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* Dangling load reservations can be the result of taking a trap in the
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* middle of an LR/SC sequence, but can also be the result of a taken
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* forward branch around an SC -- which is how we implement CAS. As a
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* result we need to clear reservations between the last CAS and the
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* jump back to the new context. While it is unlikely the store
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* completes, implementations are allowed to expand reservations to be
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* arbitrarily large.
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*/
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REG_L a2, PT_EPC(sp)
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REG_SC x0, a2, PT_EPC(sp)
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csrw CSR_STATUS, a0
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csrw CSR_EPC, a2
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REG_L x1, PT_RA(sp)
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REG_L x3, PT_GP(sp)
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REG_L x4, PT_TP(sp)
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REG_L x5, PT_T0(sp)
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restore_from_x6_to_x31
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REG_L x2, PT_SP(sp)
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#ifdef CONFIG_RISCV_M_MODE
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mret
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#else
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sret
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#endif
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SYM_CODE_END(ret_from_exception)
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ASM_NOKPROBE(ret_from_exception)
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#ifdef CONFIG_VMAP_STACK
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SYM_CODE_START_LOCAL(handle_kernel_stack_overflow)
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/* we reach here from kernel context, sscratch must be 0 */
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csrrw x31, CSR_SCRATCH, x31
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asm_per_cpu sp, overflow_stack, x31
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li x31, OVERFLOW_STACK_SIZE
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add sp, sp, x31
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/* zero out x31 again and restore x31 */
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xor x31, x31, x31
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csrrw x31, CSR_SCRATCH, x31
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addi sp, sp, -(PT_SIZE_ON_STACK)
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//save context to overflow stack
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REG_S x1, PT_RA(sp)
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REG_S x3, PT_GP(sp)
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REG_S x5, PT_T0(sp)
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save_from_x6_to_x31
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REG_L s0, TASK_TI_KERNEL_SP(tp)
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csrr s1, CSR_STATUS
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csrr s2, CSR_EPC
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csrr s3, CSR_TVAL
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csrr s4, CSR_CAUSE
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csrr s5, CSR_SCRATCH
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REG_S s0, PT_SP(sp)
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REG_S s1, PT_STATUS(sp)
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REG_S s2, PT_EPC(sp)
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REG_S s3, PT_BADADDR(sp)
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REG_S s4, PT_CAUSE(sp)
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REG_S s5, PT_TP(sp)
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move a0, sp
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tail handle_bad_stack
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SYM_CODE_END(handle_kernel_stack_overflow)
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ASM_NOKPROBE(handle_kernel_stack_overflow)
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#endif
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SYM_CODE_START(ret_from_fork)
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call schedule_tail
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beqz s0, 1f /* not from kernel thread */
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/* Call fn(arg) */
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move a0, s1
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jalr s0
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1:
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move a0, sp /* pt_regs */
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la ra, ret_from_exception
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tail syscall_exit_to_user_mode
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SYM_CODE_END(ret_from_fork)
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#ifdef CONFIG_IRQ_STACKS
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/*
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* void call_on_irq_stack(struct pt_regs *regs,
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* void (*func)(struct pt_regs *));
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*
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* Calls func(regs) using the per-CPU IRQ stack.
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*/
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SYM_FUNC_START(call_on_irq_stack)
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/* Create a frame record to save ra and s0 (fp) */
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addi sp, sp, -STACKFRAME_SIZE_ON_STACK
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REG_S ra, STACKFRAME_RA(sp)
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REG_S s0, STACKFRAME_FP(sp)
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addi s0, sp, STACKFRAME_SIZE_ON_STACK
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/* Switch to the per-CPU shadow call stack */
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scs_save_current
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scs_load_irq_stack t0
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/* Switch to the per-CPU IRQ stack and call the handler */
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load_per_cpu t0, irq_stack_ptr, t1
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li t1, IRQ_STACK_SIZE
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add sp, t0, t1
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jalr a1
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/* Switch back to the thread shadow call stack */
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scs_load_current
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/* Switch back to the thread stack and restore ra and s0 */
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addi sp, s0, -STACKFRAME_SIZE_ON_STACK
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REG_L ra, STACKFRAME_RA(sp)
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REG_L s0, STACKFRAME_FP(sp)
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addi sp, sp, STACKFRAME_SIZE_ON_STACK
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ret
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SYM_FUNC_END(call_on_irq_stack)
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#endif /* CONFIG_IRQ_STACKS */
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/*
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* Integer register context switch
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* The callee-saved registers must be saved and restored.
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*
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* a0: previous task_struct (must be preserved across the switch)
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* a1: next task_struct
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*
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* The value of a0 and a1 must be preserved by this function, as that's how
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* arguments are passed to schedule_tail.
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*/
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SYM_FUNC_START(__switch_to)
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/* Save context into prev->thread */
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li a4, TASK_THREAD_RA
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add a3, a0, a4
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add a4, a1, a4
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REG_S ra, TASK_THREAD_RA_RA(a3)
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REG_S sp, TASK_THREAD_SP_RA(a3)
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REG_S s0, TASK_THREAD_S0_RA(a3)
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REG_S s1, TASK_THREAD_S1_RA(a3)
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REG_S s2, TASK_THREAD_S2_RA(a3)
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REG_S s3, TASK_THREAD_S3_RA(a3)
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REG_S s4, TASK_THREAD_S4_RA(a3)
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REG_S s5, TASK_THREAD_S5_RA(a3)
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REG_S s6, TASK_THREAD_S6_RA(a3)
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REG_S s7, TASK_THREAD_S7_RA(a3)
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REG_S s8, TASK_THREAD_S8_RA(a3)
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REG_S s9, TASK_THREAD_S9_RA(a3)
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REG_S s10, TASK_THREAD_S10_RA(a3)
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REG_S s11, TASK_THREAD_S11_RA(a3)
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/* Save the kernel shadow call stack pointer */
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scs_save_current
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/* Restore context from next->thread */
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REG_L ra, TASK_THREAD_RA_RA(a4)
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REG_L sp, TASK_THREAD_SP_RA(a4)
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REG_L s0, TASK_THREAD_S0_RA(a4)
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REG_L s1, TASK_THREAD_S1_RA(a4)
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REG_L s2, TASK_THREAD_S2_RA(a4)
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REG_L s3, TASK_THREAD_S3_RA(a4)
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REG_L s4, TASK_THREAD_S4_RA(a4)
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REG_L s5, TASK_THREAD_S5_RA(a4)
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REG_L s6, TASK_THREAD_S6_RA(a4)
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REG_L s7, TASK_THREAD_S7_RA(a4)
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REG_L s8, TASK_THREAD_S8_RA(a4)
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REG_L s9, TASK_THREAD_S9_RA(a4)
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REG_L s10, TASK_THREAD_S10_RA(a4)
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REG_L s11, TASK_THREAD_S11_RA(a4)
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/* The offset of thread_info in task_struct is zero. */
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move tp, a1
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/* Switch to the next shadow call stack */
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scs_load_current
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ret
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SYM_FUNC_END(__switch_to)
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#ifndef CONFIG_MMU
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#define do_page_fault do_trap_unknown
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#endif
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.section ".rodata"
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.align LGREG
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/* Exception vector table */
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SYM_DATA_START_LOCAL(excp_vect_table)
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RISCV_PTR do_trap_insn_misaligned
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ALT_INSN_FAULT(RISCV_PTR do_trap_insn_fault)
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RISCV_PTR do_trap_insn_illegal
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RISCV_PTR do_trap_break
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RISCV_PTR do_trap_load_misaligned
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RISCV_PTR do_trap_load_fault
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RISCV_PTR do_trap_store_misaligned
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RISCV_PTR do_trap_store_fault
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RISCV_PTR do_trap_ecall_u /* system call */
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RISCV_PTR do_trap_ecall_s
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RISCV_PTR do_trap_unknown
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RISCV_PTR do_trap_ecall_m
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/* instruciton page fault */
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ALT_PAGE_FAULT(RISCV_PTR do_page_fault)
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RISCV_PTR do_page_fault /* load page fault */
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RISCV_PTR do_trap_unknown
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RISCV_PTR do_page_fault /* store page fault */
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SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end)
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#ifndef CONFIG_MMU
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SYM_DATA_START(__user_rt_sigreturn)
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li a7, __NR_rt_sigreturn
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ecall
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SYM_DATA_END(__user_rt_sigreturn)
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#endif
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