391 lines
9.7 KiB
C
391 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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* Copyright 2015 Regents of the University of California
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* Copyright 2017 SiFive
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*
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* Copied from arch/tile/kernel/ptrace.c
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*/
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#include <asm/vector.h>
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#include <asm/ptrace.h>
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#include <asm/syscall.h>
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#include <asm/thread_info.h>
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#include <asm/switch_to.h>
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#include <linux/audit.h>
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#include <linux/compat.h>
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#include <linux/ptrace.h>
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#include <linux/elf.h>
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#include <linux/regset.h>
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#include <linux/sched.h>
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#include <linux/sched/task_stack.h>
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enum riscv_regset {
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REGSET_X,
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#ifdef CONFIG_FPU
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REGSET_F,
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#endif
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#ifdef CONFIG_RISCV_ISA_V
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REGSET_V,
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#endif
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};
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static int riscv_gpr_get(struct task_struct *target,
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const struct user_regset *regset,
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struct membuf to)
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{
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return membuf_write(&to, task_pt_regs(target),
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sizeof(struct user_regs_struct));
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}
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static int riscv_gpr_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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struct pt_regs *regs;
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regs = task_pt_regs(target);
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return user_regset_copyin(&pos, &count, &kbuf, &ubuf, regs, 0, -1);
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}
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#ifdef CONFIG_FPU
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static int riscv_fpr_get(struct task_struct *target,
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const struct user_regset *regset,
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struct membuf to)
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{
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struct __riscv_d_ext_state *fstate = &target->thread.fstate;
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if (target == current)
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fstate_save(current, task_pt_regs(current));
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membuf_write(&to, fstate, offsetof(struct __riscv_d_ext_state, fcsr));
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membuf_store(&to, fstate->fcsr);
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return membuf_zero(&to, 4); // explicitly pad
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}
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static int riscv_fpr_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int ret;
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struct __riscv_d_ext_state *fstate = &target->thread.fstate;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, fstate, 0,
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offsetof(struct __riscv_d_ext_state, fcsr));
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if (!ret) {
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, fstate, 0,
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offsetof(struct __riscv_d_ext_state, fcsr) +
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sizeof(fstate->fcsr));
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}
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return ret;
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}
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#endif
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#ifdef CONFIG_RISCV_ISA_V
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static int riscv_vr_get(struct task_struct *target,
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const struct user_regset *regset,
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struct membuf to)
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{
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struct __riscv_v_ext_state *vstate = &target->thread.vstate;
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struct __riscv_v_regset_state ptrace_vstate;
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if (!riscv_v_vstate_query(task_pt_regs(target)))
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return -EINVAL;
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/*
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* Ensure the vector registers have been saved to the memory before
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* copying them to membuf.
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*/
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if (target == current) {
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get_cpu_vector_context();
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riscv_v_vstate_save(¤t->thread.vstate, task_pt_regs(current));
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put_cpu_vector_context();
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}
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ptrace_vstate.vstart = vstate->vstart;
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ptrace_vstate.vl = vstate->vl;
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ptrace_vstate.vtype = vstate->vtype;
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ptrace_vstate.vcsr = vstate->vcsr;
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ptrace_vstate.vlenb = vstate->vlenb;
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/* Copy vector header from vstate. */
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membuf_write(&to, &ptrace_vstate, sizeof(struct __riscv_v_regset_state));
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/* Copy all the vector registers from vstate. */
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return membuf_write(&to, vstate->datap, riscv_v_vsize);
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}
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static int riscv_vr_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int ret;
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struct __riscv_v_ext_state *vstate = &target->thread.vstate;
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struct __riscv_v_regset_state ptrace_vstate;
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if (!riscv_v_vstate_query(task_pt_regs(target)))
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return -EINVAL;
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/* Copy rest of the vstate except datap */
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ptrace_vstate, 0,
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sizeof(struct __riscv_v_regset_state));
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if (unlikely(ret))
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return ret;
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if (vstate->vlenb != ptrace_vstate.vlenb)
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return -EINVAL;
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vstate->vstart = ptrace_vstate.vstart;
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vstate->vl = ptrace_vstate.vl;
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vstate->vtype = ptrace_vstate.vtype;
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vstate->vcsr = ptrace_vstate.vcsr;
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/* Copy all the vector registers. */
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pos = 0;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap,
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0, riscv_v_vsize);
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return ret;
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}
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#endif
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static const struct user_regset riscv_user_regset[] = {
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[REGSET_X] = {
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.core_note_type = NT_PRSTATUS,
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.n = ELF_NGREG,
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.size = sizeof(elf_greg_t),
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.align = sizeof(elf_greg_t),
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.regset_get = riscv_gpr_get,
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.set = riscv_gpr_set,
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},
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#ifdef CONFIG_FPU
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[REGSET_F] = {
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.core_note_type = NT_PRFPREG,
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.n = ELF_NFPREG,
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.size = sizeof(elf_fpreg_t),
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.align = sizeof(elf_fpreg_t),
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.regset_get = riscv_fpr_get,
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.set = riscv_fpr_set,
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},
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#endif
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#ifdef CONFIG_RISCV_ISA_V
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[REGSET_V] = {
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.core_note_type = NT_RISCV_VECTOR,
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.align = 16,
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.n = ((32 * RISCV_MAX_VLENB) +
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sizeof(struct __riscv_v_regset_state)) / sizeof(__u32),
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.size = sizeof(__u32),
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.regset_get = riscv_vr_get,
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.set = riscv_vr_set,
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},
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#endif
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};
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static const struct user_regset_view riscv_user_native_view = {
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.name = "riscv",
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.e_machine = EM_RISCV,
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.regsets = riscv_user_regset,
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.n = ARRAY_SIZE(riscv_user_regset),
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};
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struct pt_regs_offset {
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const char *name;
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int offset;
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};
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#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
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#define REG_OFFSET_END {.name = NULL, .offset = 0}
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static const struct pt_regs_offset regoffset_table[] = {
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REG_OFFSET_NAME(epc),
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REG_OFFSET_NAME(ra),
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REG_OFFSET_NAME(sp),
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REG_OFFSET_NAME(gp),
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REG_OFFSET_NAME(tp),
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REG_OFFSET_NAME(t0),
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REG_OFFSET_NAME(t1),
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REG_OFFSET_NAME(t2),
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REG_OFFSET_NAME(s0),
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REG_OFFSET_NAME(s1),
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REG_OFFSET_NAME(a0),
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REG_OFFSET_NAME(a1),
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REG_OFFSET_NAME(a2),
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REG_OFFSET_NAME(a3),
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REG_OFFSET_NAME(a4),
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REG_OFFSET_NAME(a5),
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REG_OFFSET_NAME(a6),
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REG_OFFSET_NAME(a7),
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REG_OFFSET_NAME(s2),
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REG_OFFSET_NAME(s3),
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REG_OFFSET_NAME(s4),
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REG_OFFSET_NAME(s5),
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REG_OFFSET_NAME(s6),
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REG_OFFSET_NAME(s7),
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REG_OFFSET_NAME(s8),
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REG_OFFSET_NAME(s9),
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REG_OFFSET_NAME(s10),
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REG_OFFSET_NAME(s11),
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REG_OFFSET_NAME(t3),
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REG_OFFSET_NAME(t4),
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REG_OFFSET_NAME(t5),
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REG_OFFSET_NAME(t6),
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REG_OFFSET_NAME(status),
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REG_OFFSET_NAME(badaddr),
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REG_OFFSET_NAME(cause),
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REG_OFFSET_NAME(orig_a0),
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REG_OFFSET_END,
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};
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/**
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* regs_query_register_offset() - query register offset from its name
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* @name: the name of a register
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*
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* regs_query_register_offset() returns the offset of a register in struct
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* pt_regs from its name. If the name is invalid, this returns -EINVAL;
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*/
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int regs_query_register_offset(const char *name)
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{
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const struct pt_regs_offset *roff;
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for (roff = regoffset_table; roff->name != NULL; roff++)
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if (!strcmp(roff->name, name))
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return roff->offset;
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return -EINVAL;
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}
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/**
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* regs_within_kernel_stack() - check the address in the stack
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* @regs: pt_regs which contains kernel stack pointer.
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* @addr: address which is checked.
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*
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* regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
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* If @addr is within the kernel stack, it returns true. If not, returns false.
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*/
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static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
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{
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return (addr & ~(THREAD_SIZE - 1)) ==
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(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1));
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}
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/**
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* regs_get_kernel_stack_nth() - get Nth entry of the stack
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* @regs: pt_regs which contains kernel stack pointer.
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* @n: stack entry number.
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*
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* regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
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* is specified by @regs. If the @n th entry is NOT in the kernel stack,
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* this returns 0.
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*/
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unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
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{
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unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
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addr += n;
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if (regs_within_kernel_stack(regs, (unsigned long)addr))
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return *addr;
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else
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return 0;
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}
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void ptrace_disable(struct task_struct *child)
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{
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}
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long arch_ptrace(struct task_struct *child, long request,
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unsigned long addr, unsigned long data)
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{
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long ret = -EIO;
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switch (request) {
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default:
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ret = ptrace_request(child, request, addr, data);
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break;
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}
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return ret;
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}
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#ifdef CONFIG_COMPAT
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static int compat_riscv_gpr_get(struct task_struct *target,
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const struct user_regset *regset,
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struct membuf to)
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{
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struct compat_user_regs_struct cregs;
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regs_to_cregs(&cregs, task_pt_regs(target));
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return membuf_write(&to, &cregs,
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sizeof(struct compat_user_regs_struct));
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}
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static int compat_riscv_gpr_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int ret;
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struct compat_user_regs_struct cregs;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &cregs, 0, -1);
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cregs_to_regs(&cregs, task_pt_regs(target));
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return ret;
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}
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static const struct user_regset compat_riscv_user_regset[] = {
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[REGSET_X] = {
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.core_note_type = NT_PRSTATUS,
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.n = ELF_NGREG,
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.size = sizeof(compat_elf_greg_t),
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.align = sizeof(compat_elf_greg_t),
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.regset_get = compat_riscv_gpr_get,
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.set = compat_riscv_gpr_set,
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},
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#ifdef CONFIG_FPU
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[REGSET_F] = {
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.core_note_type = NT_PRFPREG,
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.n = ELF_NFPREG,
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.size = sizeof(elf_fpreg_t),
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.align = sizeof(elf_fpreg_t),
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.regset_get = riscv_fpr_get,
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.set = riscv_fpr_set,
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},
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#endif
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};
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static const struct user_regset_view compat_riscv_user_native_view = {
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.name = "riscv",
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.e_machine = EM_RISCV,
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.regsets = compat_riscv_user_regset,
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.n = ARRAY_SIZE(compat_riscv_user_regset),
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};
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long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
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compat_ulong_t caddr, compat_ulong_t cdata)
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{
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long ret = -EIO;
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switch (request) {
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default:
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ret = compat_ptrace_request(child, request, caddr, cdata);
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break;
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}
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return ret;
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}
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#else
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static const struct user_regset_view compat_riscv_user_native_view = {};
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#endif /* CONFIG_COMPAT */
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const struct user_regset_view *task_user_regset_view(struct task_struct *task)
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{
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if (is_compat_thread(&task->thread_info))
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return &compat_riscv_user_native_view;
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else
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return &riscv_user_native_view;
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}
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