649 lines
16 KiB
C
649 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 Western Digital Corporation or its affiliates.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/perf_event.h>
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#include <linux/irq.h>
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#include <linux/stringify.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/csr.h>
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#include <asm/entry-common.h>
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#include <asm/hwprobe.h>
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#include <asm/cpufeature.h>
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#define INSN_MATCH_LB 0x3
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#define INSN_MASK_LB 0x707f
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#define INSN_MATCH_LH 0x1003
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#define INSN_MASK_LH 0x707f
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#define INSN_MATCH_LW 0x2003
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#define INSN_MASK_LW 0x707f
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#define INSN_MATCH_LD 0x3003
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#define INSN_MASK_LD 0x707f
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#define INSN_MATCH_LBU 0x4003
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#define INSN_MASK_LBU 0x707f
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#define INSN_MATCH_LHU 0x5003
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#define INSN_MASK_LHU 0x707f
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#define INSN_MATCH_LWU 0x6003
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#define INSN_MASK_LWU 0x707f
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#define INSN_MATCH_SB 0x23
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#define INSN_MASK_SB 0x707f
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#define INSN_MATCH_SH 0x1023
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#define INSN_MASK_SH 0x707f
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#define INSN_MATCH_SW 0x2023
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#define INSN_MASK_SW 0x707f
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#define INSN_MATCH_SD 0x3023
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#define INSN_MASK_SD 0x707f
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#define INSN_MATCH_FLW 0x2007
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#define INSN_MASK_FLW 0x707f
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#define INSN_MATCH_FLD 0x3007
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#define INSN_MASK_FLD 0x707f
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#define INSN_MATCH_FLQ 0x4007
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#define INSN_MASK_FLQ 0x707f
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#define INSN_MATCH_FSW 0x2027
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#define INSN_MASK_FSW 0x707f
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#define INSN_MATCH_FSD 0x3027
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#define INSN_MASK_FSD 0x707f
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#define INSN_MATCH_FSQ 0x4027
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#define INSN_MASK_FSQ 0x707f
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#define INSN_MATCH_C_LD 0x6000
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#define INSN_MASK_C_LD 0xe003
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#define INSN_MATCH_C_SD 0xe000
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#define INSN_MASK_C_SD 0xe003
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#define INSN_MATCH_C_LW 0x4000
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#define INSN_MASK_C_LW 0xe003
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#define INSN_MATCH_C_SW 0xc000
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#define INSN_MASK_C_SW 0xe003
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#define INSN_MATCH_C_LDSP 0x6002
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#define INSN_MASK_C_LDSP 0xe003
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#define INSN_MATCH_C_SDSP 0xe002
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#define INSN_MASK_C_SDSP 0xe003
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#define INSN_MATCH_C_LWSP 0x4002
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#define INSN_MASK_C_LWSP 0xe003
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#define INSN_MATCH_C_SWSP 0xc002
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#define INSN_MASK_C_SWSP 0xe003
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#define INSN_MATCH_C_FLD 0x2000
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#define INSN_MASK_C_FLD 0xe003
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#define INSN_MATCH_C_FLW 0x6000
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#define INSN_MASK_C_FLW 0xe003
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#define INSN_MATCH_C_FSD 0xa000
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#define INSN_MASK_C_FSD 0xe003
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#define INSN_MATCH_C_FSW 0xe000
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#define INSN_MASK_C_FSW 0xe003
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#define INSN_MATCH_C_FLDSP 0x2002
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#define INSN_MASK_C_FLDSP 0xe003
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#define INSN_MATCH_C_FSDSP 0xa002
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#define INSN_MASK_C_FSDSP 0xe003
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#define INSN_MATCH_C_FLWSP 0x6002
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#define INSN_MASK_C_FLWSP 0xe003
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#define INSN_MATCH_C_FSWSP 0xe002
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#define INSN_MASK_C_FSWSP 0xe003
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#define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4)
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#if defined(CONFIG_64BIT)
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#define LOG_REGBYTES 3
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#define XLEN 64
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#else
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#define LOG_REGBYTES 2
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#define XLEN 32
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#endif
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#define REGBYTES (1 << LOG_REGBYTES)
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#define XLEN_MINUS_16 ((XLEN) - 16)
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#define SH_RD 7
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#define SH_RS1 15
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#define SH_RS2 20
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#define SH_RS2C 2
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#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
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#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
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(RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 5, 1) << 6))
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#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 5, 2) << 6))
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#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
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(RV_X(x, 12, 1) << 5) | \
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(RV_X(x, 2, 2) << 6))
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#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
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(RV_X(x, 12, 1) << 5) | \
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(RV_X(x, 2, 3) << 6))
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#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
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(RV_X(x, 7, 2) << 6))
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#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 7, 3) << 6))
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#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
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#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
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#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
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#define SHIFT_RIGHT(x, y) \
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((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
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#define REG_MASK \
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((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
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#define REG_OFFSET(insn, pos) \
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(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
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#define REG_PTR(insn, pos, regs) \
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(ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
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#define GET_RM(insn) (((insn) >> 12) & 7)
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#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
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#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
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#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
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#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
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#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
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#define GET_SP(regs) (*REG_PTR(2, 0, regs))
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#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
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#define IMM_I(insn) ((s32)(insn) >> 20)
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#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
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(s32)(((insn) >> 7) & 0x1f))
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#define MASK_FUNCT3 0x7000
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#define GET_PRECISION(insn) (((insn) >> 25) & 3)
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#define GET_RM(insn) (((insn) >> 12) & 7)
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#define PRECISION_S 0
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#define PRECISION_D 1
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#ifdef CONFIG_FPU
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#define FP_GET_RD(insn) (insn >> 7 & 0x1F)
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extern void put_f32_reg(unsigned long fp_reg, unsigned long value);
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static int set_f32_rd(unsigned long insn, struct pt_regs *regs,
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unsigned long val)
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{
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unsigned long fp_reg = FP_GET_RD(insn);
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put_f32_reg(fp_reg, val);
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regs->status |= SR_FS_DIRTY;
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return 0;
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}
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extern void put_f64_reg(unsigned long fp_reg, unsigned long value);
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static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val)
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{
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unsigned long fp_reg = FP_GET_RD(insn);
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unsigned long value;
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#if __riscv_xlen == 32
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value = (unsigned long) &val;
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#else
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value = val;
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#endif
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put_f64_reg(fp_reg, value);
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regs->status |= SR_FS_DIRTY;
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return 0;
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}
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#if __riscv_xlen == 32
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extern void get_f64_reg(unsigned long fp_reg, u64 *value);
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static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset,
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struct pt_regs *regs)
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{
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unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F;
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u64 val;
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get_f64_reg(fp_reg, &val);
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regs->status |= SR_FS_DIRTY;
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return val;
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}
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#else
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extern unsigned long get_f64_reg(unsigned long fp_reg);
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static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,
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struct pt_regs *regs)
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{
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unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F;
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unsigned long val;
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val = get_f64_reg(fp_reg);
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regs->status |= SR_FS_DIRTY;
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return val;
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}
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#endif
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extern unsigned long get_f32_reg(unsigned long fp_reg);
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static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset,
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struct pt_regs *regs)
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{
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unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F;
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unsigned long val;
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val = get_f32_reg(fp_reg);
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regs->status |= SR_FS_DIRTY;
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return val;
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}
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#else /* CONFIG_FPU */
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static void set_f32_rd(unsigned long insn, struct pt_regs *regs,
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unsigned long val) {}
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static void set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) {}
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static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,
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struct pt_regs *regs)
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{
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return 0;
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}
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static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset,
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struct pt_regs *regs)
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{
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return 0;
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}
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#endif
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#define GET_F64_RS2(insn, regs) (get_f64_rs(insn, 20, regs))
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#define GET_F64_RS2C(insn, regs) (get_f64_rs(insn, 2, regs))
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#define GET_F64_RS2S(insn, regs) (get_f64_rs(RVC_RS2S(insn), 0, regs))
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#define GET_F32_RS2(insn, regs) (get_f32_rs(insn, 20, regs))
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#define GET_F32_RS2C(insn, regs) (get_f32_rs(insn, 2, regs))
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#define GET_F32_RS2S(insn, regs) (get_f32_rs(RVC_RS2S(insn), 0, regs))
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#ifdef CONFIG_RISCV_M_MODE
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static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val)
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{
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u8 val;
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asm volatile("lbu %0, %1" : "=&r" (val) : "m" (*addr));
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*r_val = val;
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return 0;
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}
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static inline int store_u8(struct pt_regs *regs, u8 *addr, u8 val)
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{
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asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr));
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return 0;
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}
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static inline int get_insn(struct pt_regs *regs, ulong mepc, ulong *r_insn)
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{
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register ulong __mepc asm ("a2") = mepc;
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ulong val, rvc_mask = 3, tmp;
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asm ("and %[tmp], %[addr], 2\n"
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"bnez %[tmp], 1f\n"
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#if defined(CONFIG_64BIT)
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__stringify(LWU) " %[insn], (%[addr])\n"
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#else
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__stringify(LW) " %[insn], (%[addr])\n"
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#endif
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"and %[tmp], %[insn], %[rvc_mask]\n"
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"beq %[tmp], %[rvc_mask], 2f\n"
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"sll %[insn], %[insn], %[xlen_minus_16]\n"
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"srl %[insn], %[insn], %[xlen_minus_16]\n"
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"j 2f\n"
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"1:\n"
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"lhu %[insn], (%[addr])\n"
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"and %[tmp], %[insn], %[rvc_mask]\n"
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"bne %[tmp], %[rvc_mask], 2f\n"
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"lhu %[tmp], 2(%[addr])\n"
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"sll %[tmp], %[tmp], 16\n"
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"add %[insn], %[insn], %[tmp]\n"
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"2:"
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: [insn] "=&r" (val), [tmp] "=&r" (tmp)
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: [addr] "r" (__mepc), [rvc_mask] "r" (rvc_mask),
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[xlen_minus_16] "i" (XLEN_MINUS_16));
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*r_insn = val;
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return 0;
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}
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#else
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static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val)
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{
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if (user_mode(regs)) {
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return __get_user(*r_val, (u8 __user *)addr);
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} else {
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*r_val = *addr;
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return 0;
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}
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}
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static inline int store_u8(struct pt_regs *regs, u8 *addr, u8 val)
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{
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if (user_mode(regs)) {
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return __put_user(val, (u8 __user *)addr);
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} else {
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*addr = val;
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return 0;
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}
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}
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#define __read_insn(regs, insn, insn_addr) \
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({ \
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int __ret; \
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\
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if (user_mode(regs)) { \
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__ret = __get_user(insn, insn_addr); \
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} else { \
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insn = *(__force u16 *)insn_addr; \
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__ret = 0; \
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} \
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\
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__ret; \
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})
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static inline int get_insn(struct pt_regs *regs, ulong epc, ulong *r_insn)
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{
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ulong insn = 0;
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if (epc & 0x2) {
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ulong tmp = 0;
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u16 __user *insn_addr = (u16 __user *)epc;
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if (__read_insn(regs, insn, insn_addr))
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return -EFAULT;
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/* __get_user() uses regular "lw" which sign extend the loaded
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* value make sure to clear higher order bits in case we "or" it
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* below with the upper 16 bits half.
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*/
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insn &= GENMASK(15, 0);
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if ((insn & __INSN_LENGTH_MASK) != __INSN_LENGTH_32) {
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*r_insn = insn;
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return 0;
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}
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insn_addr++;
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if (__read_insn(regs, tmp, insn_addr))
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return -EFAULT;
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*r_insn = (tmp << 16) | insn;
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return 0;
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} else {
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u32 __user *insn_addr = (u32 __user *)epc;
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if (__read_insn(regs, insn, insn_addr))
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return -EFAULT;
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if ((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) {
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*r_insn = insn;
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return 0;
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}
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insn &= GENMASK(15, 0);
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*r_insn = insn;
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return 0;
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}
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}
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#endif
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union reg_data {
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u8 data_bytes[8];
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ulong data_ulong;
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u64 data_u64;
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};
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static bool unaligned_ctl __read_mostly;
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/* sysctl hooks */
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int unaligned_enabled __read_mostly = 1; /* Enabled by default */
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int handle_misaligned_load(struct pt_regs *regs)
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{
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union reg_data val;
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unsigned long epc = regs->epc;
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unsigned long insn;
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unsigned long addr = regs->badaddr;
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int i, fp = 0, shift = 0, len = 0;
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perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
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#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS
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*this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_EMULATED;
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#endif
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if (!unaligned_enabled)
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return -1;
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if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS))
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return -1;
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if (get_insn(regs, epc, &insn))
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return -1;
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regs->epc = 0;
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if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
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len = 4;
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shift = 8 * (sizeof(unsigned long) - len);
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#if defined(CONFIG_64BIT)
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} else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {
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len = 8;
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shift = 8 * (sizeof(unsigned long) - len);
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} else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {
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len = 4;
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#endif
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} else if ((insn & INSN_MASK_FLD) == INSN_MATCH_FLD) {
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fp = 1;
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len = 8;
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} else if ((insn & INSN_MASK_FLW) == INSN_MATCH_FLW) {
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fp = 1;
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len = 4;
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} else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {
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len = 2;
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shift = 8 * (sizeof(unsigned long) - len);
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} else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
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len = 2;
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#if defined(CONFIG_64BIT)
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} else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
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len = 8;
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shift = 8 * (sizeof(unsigned long) - len);
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insn = RVC_RS2S(insn) << SH_RD;
|
|
} else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&
|
|
((insn >> SH_RD) & 0x1f)) {
|
|
len = 8;
|
|
shift = 8 * (sizeof(unsigned long) - len);
|
|
#endif
|
|
} else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {
|
|
len = 4;
|
|
shift = 8 * (sizeof(unsigned long) - len);
|
|
insn = RVC_RS2S(insn) << SH_RD;
|
|
} else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&
|
|
((insn >> SH_RD) & 0x1f)) {
|
|
len = 4;
|
|
shift = 8 * (sizeof(unsigned long) - len);
|
|
} else if ((insn & INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) {
|
|
fp = 1;
|
|
len = 8;
|
|
insn = RVC_RS2S(insn) << SH_RD;
|
|
} else if ((insn & INSN_MASK_C_FLDSP) == INSN_MATCH_C_FLDSP) {
|
|
fp = 1;
|
|
len = 8;
|
|
#if defined(CONFIG_32BIT)
|
|
} else if ((insn & INSN_MASK_C_FLW) == INSN_MATCH_C_FLW) {
|
|
fp = 1;
|
|
len = 4;
|
|
insn = RVC_RS2S(insn) << SH_RD;
|
|
} else if ((insn & INSN_MASK_C_FLWSP) == INSN_MATCH_C_FLWSP) {
|
|
fp = 1;
|
|
len = 4;
|
|
#endif
|
|
} else {
|
|
regs->epc = epc;
|
|
return -1;
|
|
}
|
|
|
|
if (!IS_ENABLED(CONFIG_FPU) && fp)
|
|
return -EOPNOTSUPP;
|
|
|
|
val.data_u64 = 0;
|
|
for (i = 0; i < len; i++) {
|
|
if (load_u8(regs, (void *)(addr + i), &val.data_bytes[i]))
|
|
return -1;
|
|
}
|
|
|
|
if (!fp)
|
|
SET_RD(insn, regs, val.data_ulong << shift >> shift);
|
|
else if (len == 8)
|
|
set_f64_rd(insn, regs, val.data_u64);
|
|
else
|
|
set_f32_rd(insn, regs, val.data_ulong);
|
|
|
|
regs->epc = epc + INSN_LEN(insn);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int handle_misaligned_store(struct pt_regs *regs)
|
|
{
|
|
union reg_data val;
|
|
unsigned long epc = regs->epc;
|
|
unsigned long insn;
|
|
unsigned long addr = regs->badaddr;
|
|
int i, len = 0, fp = 0;
|
|
|
|
perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
|
|
|
|
if (!unaligned_enabled)
|
|
return -1;
|
|
|
|
if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS))
|
|
return -1;
|
|
|
|
if (get_insn(regs, epc, &insn))
|
|
return -1;
|
|
|
|
regs->epc = 0;
|
|
|
|
val.data_ulong = GET_RS2(insn, regs);
|
|
|
|
if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) {
|
|
len = 4;
|
|
#if defined(CONFIG_64BIT)
|
|
} else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) {
|
|
len = 8;
|
|
#endif
|
|
} else if ((insn & INSN_MASK_FSD) == INSN_MATCH_FSD) {
|
|
fp = 1;
|
|
len = 8;
|
|
val.data_u64 = GET_F64_RS2(insn, regs);
|
|
} else if ((insn & INSN_MASK_FSW) == INSN_MATCH_FSW) {
|
|
fp = 1;
|
|
len = 4;
|
|
val.data_ulong = GET_F32_RS2(insn, regs);
|
|
} else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
|
|
len = 2;
|
|
#if defined(CONFIG_64BIT)
|
|
} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
|
|
len = 8;
|
|
val.data_ulong = GET_RS2S(insn, regs);
|
|
} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP) {
|
|
len = 8;
|
|
val.data_ulong = GET_RS2C(insn, regs);
|
|
#endif
|
|
} else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
|
|
len = 4;
|
|
val.data_ulong = GET_RS2S(insn, regs);
|
|
} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP) {
|
|
len = 4;
|
|
val.data_ulong = GET_RS2C(insn, regs);
|
|
} else if ((insn & INSN_MASK_C_FSD) == INSN_MATCH_C_FSD) {
|
|
fp = 1;
|
|
len = 8;
|
|
val.data_u64 = GET_F64_RS2S(insn, regs);
|
|
} else if ((insn & INSN_MASK_C_FSDSP) == INSN_MATCH_C_FSDSP) {
|
|
fp = 1;
|
|
len = 8;
|
|
val.data_u64 = GET_F64_RS2C(insn, regs);
|
|
#if !defined(CONFIG_64BIT)
|
|
} else if ((insn & INSN_MASK_C_FSW) == INSN_MATCH_C_FSW) {
|
|
fp = 1;
|
|
len = 4;
|
|
val.data_ulong = GET_F32_RS2S(insn, regs);
|
|
} else if ((insn & INSN_MASK_C_FSWSP) == INSN_MATCH_C_FSWSP) {
|
|
fp = 1;
|
|
len = 4;
|
|
val.data_ulong = GET_F32_RS2C(insn, regs);
|
|
#endif
|
|
} else {
|
|
regs->epc = epc;
|
|
return -1;
|
|
}
|
|
|
|
if (!IS_ENABLED(CONFIG_FPU) && fp)
|
|
return -EOPNOTSUPP;
|
|
|
|
for (i = 0; i < len; i++) {
|
|
if (store_u8(regs, (void *)(addr + i), val.data_bytes[i]))
|
|
return -1;
|
|
}
|
|
|
|
regs->epc = epc + INSN_LEN(insn);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool check_unaligned_access_emulated(int cpu)
|
|
{
|
|
long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu);
|
|
unsigned long tmp_var, tmp_val;
|
|
bool misaligned_emu_detected;
|
|
|
|
*mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
|
|
|
|
__asm__ __volatile__ (
|
|
" "REG_L" %[tmp], 1(%[ptr])\n"
|
|
: [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory");
|
|
|
|
misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED);
|
|
/*
|
|
* If unaligned_ctl is already set, this means that we detected that all
|
|
* CPUS uses emulated misaligned access at boot time. If that changed
|
|
* when hotplugging the new cpu, this is something we don't handle.
|
|
*/
|
|
if (unlikely(unaligned_ctl && !misaligned_emu_detected)) {
|
|
pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)\n");
|
|
while (true)
|
|
cpu_relax();
|
|
}
|
|
|
|
return misaligned_emu_detected;
|
|
}
|
|
|
|
bool check_unaligned_access_emulated_all_cpus(void)
|
|
{
|
|
int cpu;
|
|
|
|
/*
|
|
* We can only support PR_UNALIGN controls if all CPUs have misaligned
|
|
* accesses emulated since tasks requesting such control can run on any
|
|
* CPU.
|
|
*/
|
|
for_each_online_cpu(cpu)
|
|
if (!check_unaligned_access_emulated(cpu))
|
|
return false;
|
|
|
|
unaligned_ctl = true;
|
|
return true;
|
|
}
|
|
|
|
bool unaligned_ctl_available(void)
|
|
{
|
|
return unaligned_ctl;
|
|
}
|