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23c671be97
Mark of the Unicorn (MOTU) shipped 896HD 2003 as one of models in second
generation of its FireWire series, and already discontinued it. The model
consists of below ICs:
* Texas Instruments TSB41AB2
* Phillips Semiconductors PDI1394L40
* Altera cyclone EP1C3
* Texas Instruments TMS320VC5402
It supports sampling transmission frequency up to 192.0 kHz. The packet
format differs depending on both of sampling transfer frequency and enabling
ADAT channels. The model doesn't support MIDI message transmission.
This commit adds support for it.
$ python3 crpp < /sys/bus/firewire/devices/fw1/config_rom
ROM header and bus information block
-----------------------------------------------------------------
400 04101b66 bus_info_length 4, crc_length 16, crc 7014
404 31333934 bus_name "1394"
408 20001000 irmc 0, cmc 0, isc 1, bmc 0, cyc_clk_acc 0, max_rec 1 (4)
40c 0001f200 company_id 0001f2 |
410 0001dbce device_id 000001dbce | EUI-64 0001f2000001dbce
root directory
-----------------------------------------------------------------
414 0004c65c directory_length 4, crc 50780
418 030001f2 vendor
41c 0c0083c0 node capabilities per IEEE 1394
420 8d000006 --> eui-64 leaf at 438
424 d1000001 --> unit directory at 428
unit directory at 428
-----------------------------------------------------------------
428 0003dcc1 directory_length 3, crc 56513
42c 120001f2 specifier id
430 13000005 version
434 17102800 model
eui-64 leaf at 438
-----------------------------------------------------------------
438 000264f2 leaf_length 2, crc 25842
43c 0001f200 company_id 0001f2 |
440 0001dbce device_id 000001dbce | EUI-64 0001f2000001dbce
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Link: https://lore.kernel.org/r/20210823085741.33864-1-o-takashi@sakamocchi.jp
Signed-off-by: Takashi Iwai <tiwai@suse.de>
317 lines
8.2 KiB
C
317 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* motu-protocol-v2.c - a part of driver for MOTU FireWire series
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*
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* Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
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*/
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#include "motu.h"
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#define V2_CLOCK_STATUS_OFFSET 0x0b14
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#define V2_CLOCK_RATE_MASK 0x00000038
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#define V2_CLOCK_RATE_SHIFT 3
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#define V2_CLOCK_SRC_MASK 0x00000007
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#define V2_CLOCK_SRC_SHIFT 0
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#define V2_CLOCK_SRC_AESEBU_ON_XLR 0x07 // In Traveler.
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#define V2_CLOCK_SRC_ADAT_ON_DSUB 0x05
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#define V2_CLOCK_SRC_WORD_ON_BNC 0x04
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#define V2_CLOCK_SRC_SPH 0x03
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#define V2_CLOCK_SRC_SPDIF 0x02 // on either coaxial or optical. AES/EBU in 896HD.
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#define V2_CLOCK_SRC_ADAT_ON_OPT 0x01
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#define V2_CLOCK_SRC_INTERNAL 0x00
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#define V2_CLOCK_FETCH_ENABLE 0x02000000
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#define V2_CLOCK_MODEL_SPECIFIC 0x04000000
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#define V2_IN_OUT_CONF_OFFSET 0x0c04
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#define V2_OPT_OUT_IFACE_MASK 0x00000c00
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#define V2_OPT_OUT_IFACE_SHIFT 10
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#define V2_OPT_IN_IFACE_MASK 0x00000300
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#define V2_OPT_IN_IFACE_SHIFT 8
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#define V2_OPT_IFACE_MODE_NONE 0
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#define V2_OPT_IFACE_MODE_ADAT 1
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#define V2_OPT_IFACE_MODE_SPDIF 2
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static int get_clock_rate(u32 data, unsigned int *rate)
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{
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unsigned int index = (data & V2_CLOCK_RATE_MASK) >> V2_CLOCK_RATE_SHIFT;
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if (index >= ARRAY_SIZE(snd_motu_clock_rates))
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return -EIO;
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*rate = snd_motu_clock_rates[index];
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return 0;
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}
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int snd_motu_protocol_v2_get_clock_rate(struct snd_motu *motu,
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unsigned int *rate)
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{
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__be32 reg;
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int err;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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return get_clock_rate(be32_to_cpu(reg), rate);
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}
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int snd_motu_protocol_v2_set_clock_rate(struct snd_motu *motu,
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unsigned int rate)
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{
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__be32 reg;
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u32 data;
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int i;
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int err;
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for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) {
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if (snd_motu_clock_rates[i] == rate)
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break;
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}
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if (i == ARRAY_SIZE(snd_motu_clock_rates))
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return -EINVAL;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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data &= ~V2_CLOCK_RATE_MASK;
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data |= i << V2_CLOCK_RATE_SHIFT;
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reg = cpu_to_be32(data);
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return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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}
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static int get_clock_source(struct snd_motu *motu, u32 data,
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enum snd_motu_clock_source *src)
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{
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switch (data & V2_CLOCK_SRC_MASK) {
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case V2_CLOCK_SRC_INTERNAL:
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*src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
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break;
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case V2_CLOCK_SRC_ADAT_ON_OPT:
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*src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
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break;
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case V2_CLOCK_SRC_SPDIF:
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{
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bool support_iec60958_on_opt = (motu->spec == &snd_motu_spec_828mk2 ||
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motu->spec == &snd_motu_spec_traveler);
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if (motu->spec == &snd_motu_spec_896hd) {
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*src = SND_MOTU_CLOCK_SOURCE_AESEBU_ON_XLR;
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} else if (!support_iec60958_on_opt) {
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
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} else {
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__be32 reg;
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// To check the configuration of optical interface.
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int err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) ==
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V2_OPT_IFACE_MODE_SPDIF)
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT;
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else
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
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}
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break;
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}
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case V2_CLOCK_SRC_SPH:
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*src = SND_MOTU_CLOCK_SOURCE_SPH;
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break;
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case V2_CLOCK_SRC_WORD_ON_BNC:
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*src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
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break;
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case V2_CLOCK_SRC_ADAT_ON_DSUB:
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*src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
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break;
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case V2_CLOCK_SRC_AESEBU_ON_XLR:
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// For Traveler.
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*src = SND_MOTU_CLOCK_SOURCE_AESEBU_ON_XLR;
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break;
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default:
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*src = SND_MOTU_CLOCK_SOURCE_UNKNOWN;
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break;
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}
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return 0;
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}
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int snd_motu_protocol_v2_get_clock_source(struct snd_motu *motu,
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enum snd_motu_clock_source *src)
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{
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__be32 reg;
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int err;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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return get_clock_source(motu, be32_to_cpu(reg), src);
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}
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// Expected for Traveler, which implements Altera Cyclone EP1C3.
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static int switch_fetching_mode_cyclone(struct snd_motu *motu, u32 *data,
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bool enable)
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{
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*data |= V2_CLOCK_MODEL_SPECIFIC;
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return 0;
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}
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// For UltraLite and 8pre, which implements Xilinx Spartan XC3S200.
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static int switch_fetching_mode_spartan(struct snd_motu *motu, u32 *data,
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bool enable)
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{
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unsigned int rate;
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enum snd_motu_clock_source src;
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int err;
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err = get_clock_source(motu, *data, &src);
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if (err < 0)
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return err;
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err = get_clock_rate(*data, &rate);
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if (err < 0)
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return err;
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if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000)
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*data |= V2_CLOCK_MODEL_SPECIFIC;
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return 0;
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}
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int snd_motu_protocol_v2_switch_fetching_mode(struct snd_motu *motu,
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bool enable)
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{
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if (motu->spec == &snd_motu_spec_828mk2) {
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// 828mkII implements Altera ACEX 1K EP1K30. Nothing to do.
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return 0;
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} else if (motu->spec == &snd_motu_spec_896hd) {
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// 896HD implements Altera Cyclone EP1C3 but nothing to do.
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return 0;
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} else {
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__be32 reg;
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u32 data;
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int err;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET,
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®, sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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data &= ~(V2_CLOCK_FETCH_ENABLE | V2_CLOCK_MODEL_SPECIFIC);
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if (enable)
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data |= V2_CLOCK_FETCH_ENABLE;
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if (motu->spec == &snd_motu_spec_traveler)
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err = switch_fetching_mode_cyclone(motu, &data, enable);
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else
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err = switch_fetching_mode_spartan(motu, &data, enable);
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if (err < 0)
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return err;
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reg = cpu_to_be32(data);
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return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET,
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®, sizeof(reg));
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}
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}
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int snd_motu_protocol_v2_cache_packet_formats(struct snd_motu *motu)
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{
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bool has_two_opt_ifaces = (motu->spec == &snd_motu_spec_8pre);
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__be32 reg;
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u32 data;
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int err;
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motu->tx_packet_formats.pcm_byte_offset = 10;
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motu->rx_packet_formats.pcm_byte_offset = 10;
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motu->tx_packet_formats.msg_chunks = 2;
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motu->rx_packet_formats.msg_chunks = 2;
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err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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memcpy(motu->tx_packet_formats.pcm_chunks,
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motu->spec->tx_fixed_pcm_chunks,
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sizeof(motu->tx_packet_formats.pcm_chunks));
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memcpy(motu->rx_packet_formats.pcm_chunks,
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motu->spec->rx_fixed_pcm_chunks,
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sizeof(motu->rx_packet_formats.pcm_chunks));
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if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) == V2_OPT_IFACE_MODE_ADAT) {
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motu->tx_packet_formats.pcm_chunks[0] += 8;
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if (!has_two_opt_ifaces)
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motu->tx_packet_formats.pcm_chunks[1] += 4;
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else
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motu->tx_packet_formats.pcm_chunks[1] += 8;
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}
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if (((data & V2_OPT_OUT_IFACE_MASK) >> V2_OPT_OUT_IFACE_SHIFT) == V2_OPT_IFACE_MODE_ADAT) {
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motu->rx_packet_formats.pcm_chunks[0] += 8;
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if (!has_two_opt_ifaces)
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motu->rx_packet_formats.pcm_chunks[1] += 4;
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else
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motu->rx_packet_formats.pcm_chunks[1] += 8;
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}
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return 0;
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}
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const struct snd_motu_spec snd_motu_spec_828mk2 = {
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.name = "828mk2",
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.protocol_version = SND_MOTU_PROTOCOL_V2,
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.flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
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SND_MOTU_SPEC_TX_MIDI_2ND_Q,
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.tx_fixed_pcm_chunks = {14, 14, 0},
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.rx_fixed_pcm_chunks = {14, 14, 0},
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};
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const struct snd_motu_spec snd_motu_spec_896hd = {
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.name = "896HD",
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.protocol_version = SND_MOTU_PROTOCOL_V2,
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// No support for MIDI.
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.tx_fixed_pcm_chunks = {14, 14, 8},
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.rx_fixed_pcm_chunks = {14, 14, 8},
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};
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const struct snd_motu_spec snd_motu_spec_traveler = {
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.name = "Traveler",
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.protocol_version = SND_MOTU_PROTOCOL_V2,
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.flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
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SND_MOTU_SPEC_TX_MIDI_2ND_Q,
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.tx_fixed_pcm_chunks = {14, 14, 8},
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.rx_fixed_pcm_chunks = {14, 14, 8},
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};
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const struct snd_motu_spec snd_motu_spec_ultralite = {
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.name = "UltraLite",
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.protocol_version = SND_MOTU_PROTOCOL_V2,
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.flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
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SND_MOTU_SPEC_TX_MIDI_2ND_Q,
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.tx_fixed_pcm_chunks = {14, 14, 0},
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.rx_fixed_pcm_chunks = {14, 14, 0},
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};
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const struct snd_motu_spec snd_motu_spec_8pre = {
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.name = "8pre",
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.protocol_version = SND_MOTU_PROTOCOL_V2,
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.flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
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SND_MOTU_SPEC_TX_MIDI_2ND_Q,
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// Two dummy chunks always in the end of data block.
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.tx_fixed_pcm_chunks = {10, 10, 0},
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.rx_fixed_pcm_chunks = {6, 6, 0},
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};
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