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![Ville Syrjälä](/assets/img/avatar_default.png)
Pull the IPS state readout into hsw_ips.c. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220209113526.7595-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
271 lines
7.5 KiB
C
271 lines
7.5 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "hsw_ips.h"
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_pcode.h"
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static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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if (!crtc_state->ips_enabled)
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return;
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/*
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* We can only enable IPS after we enable a plane and wait for a vblank
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* This function is called from post_plane_update, which is run after
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* a vblank wait.
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*/
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drm_WARN_ON(&i915->drm,
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!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
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if (IS_BROADWELL(i915)) {
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drm_WARN_ON(&i915->drm,
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snb_pcode_write(i915, DISPLAY_IPS_CONTROL,
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IPS_ENABLE | IPS_PCODE_CONTROL));
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/*
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* Quoting Art Runyan: "its not safe to expect any particular
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* value in IPS_CTL bit 31 after enabling IPS through the
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* mailbox." Moreover, the mailbox may return a bogus state,
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* so we need to just enable it and continue on.
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*/
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} else {
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intel_de_write(i915, IPS_CTL, IPS_ENABLE);
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/*
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* The bit only becomes 1 in the next vblank, so this wait here
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* is essentially intel_wait_for_vblank. If we don't have this
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* and don't wait for vblanks until the end of crtc_enable, then
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* the HW state readout code will complain that the expected
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* IPS_CTL value is not the one we read.
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*/
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if (intel_de_wait_for_set(i915, IPS_CTL, IPS_ENABLE, 50))
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drm_err(&i915->drm,
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"Timed out waiting for IPS enable\n");
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}
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}
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bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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bool need_vblank_wait = false;
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if (!crtc_state->ips_enabled)
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return need_vblank_wait;
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if (IS_BROADWELL(i915)) {
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drm_WARN_ON(&i915->drm,
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snb_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));
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/*
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* Wait for PCODE to finish disabling IPS. The BSpec specified
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* 42ms timeout value leads to occasional timeouts so use 100ms
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* instead.
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*/
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if (intel_de_wait_for_clear(i915, IPS_CTL, IPS_ENABLE, 100))
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drm_err(&i915->drm,
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"Timed out waiting for IPS disable\n");
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} else {
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intel_de_write(i915, IPS_CTL, 0);
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intel_de_posting_read(i915, IPS_CTL);
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}
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/* We need to wait for a vblank before we can disable the plane. */
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need_vblank_wait = true;
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return need_vblank_wait;
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}
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static bool hsw_ips_need_disable(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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const struct intel_crtc_state *old_crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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const struct intel_crtc_state *new_crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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if (!old_crtc_state->ips_enabled)
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return false;
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if (intel_crtc_needs_modeset(new_crtc_state))
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return true;
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/*
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* Workaround : Do not read or write the pipe palette/gamma data while
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* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
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*
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* Disable IPS before we program the LUT.
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*/
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if (IS_HASWELL(i915) &&
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(new_crtc_state->uapi.color_mgmt_changed ||
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new_crtc_state->update_pipe) &&
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new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
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return true;
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return !new_crtc_state->ips_enabled;
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}
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bool hsw_ips_pre_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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const struct intel_crtc_state *old_crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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if (!hsw_ips_need_disable(state, crtc))
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return false;
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return hsw_ips_disable(old_crtc_state);
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}
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static bool hsw_ips_need_enable(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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const struct intel_crtc_state *old_crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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const struct intel_crtc_state *new_crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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if (!new_crtc_state->ips_enabled)
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return false;
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if (intel_crtc_needs_modeset(new_crtc_state))
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return true;
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/*
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* Workaround : Do not read or write the pipe palette/gamma data while
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* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
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*
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* Re-enable IPS after the LUT has been programmed.
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*/
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if (IS_HASWELL(i915) &&
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(new_crtc_state->uapi.color_mgmt_changed ||
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new_crtc_state->update_pipe) &&
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new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
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return true;
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/*
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* We can't read out IPS on broadwell, assume the worst and
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* forcibly enable IPS on the first fastset.
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*/
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if (new_crtc_state->update_pipe && old_crtc_state->inherited)
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return true;
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return !old_crtc_state->ips_enabled;
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}
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void hsw_ips_post_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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const struct intel_crtc_state *new_crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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if (!hsw_ips_need_enable(state, crtc))
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return;
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hsw_ips_enable(new_crtc_state);
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}
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/* IPS only exists on ULT machines and is tied to pipe A. */
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bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
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{
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return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
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}
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bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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/* IPS only exists on ULT machines and is tied to pipe A. */
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if (!hsw_crtc_supports_ips(crtc))
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return false;
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if (!i915->params.enable_ips)
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return false;
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if (crtc_state->pipe_bpp > 24)
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return false;
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/*
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* We compare against max which means we must take
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* the increased cdclk requirement into account when
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* calculating the new cdclk.
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*
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* Should measure whether using a lower cdclk w/o IPS
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*/
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if (IS_BROADWELL(i915) &&
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crtc_state->pixel_rate > i915->max_cdclk_freq * 95 / 100)
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return false;
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return true;
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}
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int hsw_ips_compute_config(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *i915 = to_i915(state->base.dev);
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struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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crtc_state->ips_enabled = false;
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if (!hsw_crtc_state_ips_capable(crtc_state))
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return 0;
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/*
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* When IPS gets enabled, the pipe CRC changes. Since IPS gets
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* enabled and disabled dynamically based on package C states,
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* user space can't make reliable use of the CRCs, so let's just
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* completely disable it.
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*/
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if (crtc_state->crc_enabled)
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return 0;
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/* IPS should be fine as long as at least one plane is enabled. */
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if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
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return 0;
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if (IS_BROADWELL(i915)) {
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const struct intel_cdclk_state *cdclk_state;
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cdclk_state = intel_atomic_get_cdclk_state(state);
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if (IS_ERR(cdclk_state))
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return PTR_ERR(cdclk_state);
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/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
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if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
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return 0;
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}
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crtc_state->ips_enabled = true;
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return 0;
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}
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void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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if (!hsw_crtc_supports_ips(crtc))
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return;
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if (IS_HASWELL(i915)) {
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crtc_state->ips_enabled = intel_de_read(i915, IPS_CTL) & IPS_ENABLE;
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} else {
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/*
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* We cannot readout IPS state on broadwell, set to
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* true so we can set it to a defined state on first
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* commit.
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*/
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crtc_state->ips_enabled = true;
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}
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}
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