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![Ville Syrjälä](/assets/img/avatar_default.png)
Make life simpler by always programming DP M2/N2 with a consistent value. This will lets use do state readout+chec unconditionally. I was first going to just set M2/N2=M1/N1 but then it occurred to me that it might interfere with fastboot on account of BIOS likely leaving the registers zeroed. So let's zero out the values instead (except TU where a zero register value actually means '1'). Still not sure that's the best approach but lets go with it for now. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-14-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
464 lines
13 KiB
C
464 lines
13 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_atomic.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_drrs.h"
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#include "intel_panel.h"
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/**
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* DOC: Display Refresh Rate Switching (DRRS)
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*
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* Display Refresh Rate Switching (DRRS) is a power conservation feature
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* which enables swtching between low and high refresh rates,
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* dynamically, based on the usage scenario. This feature is applicable
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* for internal panels.
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*
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* Indication that the panel supports DRRS is given by the panel EDID, which
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* would list multiple refresh rates for one resolution.
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*
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* DRRS is of 2 types - static and seamless.
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* Static DRRS involves changing refresh rate (RR) by doing a full modeset
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* (may appear as a blink on screen) and is used in dock-undock scenario.
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* Seamless DRRS involves changing RR without any visual effect to the user
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* and can be used during normal system usage. This is done by programming
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* certain registers.
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*
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* Support for static/seamless DRRS may be indicated in the VBT based on
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* inputs from the panel spec.
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*
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* DRRS saves power by switching to low RR based on usage scenarios.
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*
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* The implementation is based on frontbuffer tracking implementation. When
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* there is a disturbance on the screen triggered by user activity or a periodic
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* system activity, DRRS is disabled (RR is changed to high RR). When there is
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* no movement on screen, after a timeout of 1 second, a switch to low RR is
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* made.
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*
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* For integration with frontbuffer tracking code, intel_drrs_invalidate()
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* and intel_drrs_flush() are called.
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*
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* DRRS can be further extended to support other internal panels and also
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* the scenario of video playback wherein RR is set based on the rate
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* requested by userspace.
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*/
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static bool can_enable_drrs(struct intel_connector *connector,
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const struct intel_crtc_state *pipe_config)
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{
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const struct drm_i915_private *i915 = to_i915(connector->base.dev);
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if (pipe_config->vrr.enable)
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return false;
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/*
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* DRRS and PSR can't be enable together, so giving preference to PSR
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* as it allows more power-savings by complete shutting down display,
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* so to guarantee this, intel_drrs_compute_config() must be called
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* after intel_psr_compute_config().
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*/
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if (pipe_config->has_psr)
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return false;
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return connector->panel.downclock_mode &&
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i915->drrs.type == SEAMLESS_DRRS_SUPPORT;
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}
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void
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intel_drrs_compute_config(struct intel_dp *intel_dp,
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struct intel_crtc_state *pipe_config,
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int output_bpp, bool constant_n)
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{
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struct intel_connector *connector = intel_dp->attached_connector;
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struct drm_i915_private *i915 = to_i915(connector->base.dev);
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int pixel_clock;
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if (!can_enable_drrs(connector, pipe_config)) {
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if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
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intel_zero_m_n(&pipe_config->dp_m2_n2);
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return;
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}
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pipe_config->has_drrs = true;
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pixel_clock = connector->panel.downclock_mode->clock;
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if (pipe_config->splitter.enable)
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pixel_clock /= pipe_config->splitter.link_count;
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intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
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pipe_config->port_clock, &pipe_config->dp_m2_n2,
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constant_n, pipe_config->fec_enable);
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/* FIXME: abstract this better */
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if (pipe_config->splitter.enable)
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pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
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}
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static void
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intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state,
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enum drrs_refresh_rate_type refresh_type)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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u32 val, bit;
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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bit = PIPECONF_EDP_RR_MODE_SWITCH_VLV;
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else
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bit = PIPECONF_EDP_RR_MODE_SWITCH;
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val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
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if (refresh_type == DRRS_LOW_RR)
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val |= bit;
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else
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val &= ~bit;
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intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
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}
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static void
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intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state,
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enum drrs_refresh_rate_type refresh_type)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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intel_cpu_transcoder_set_m1_n1(crtc, crtc_state->cpu_transcoder,
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refresh_type == DRRS_LOW_RR ?
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&crtc_state->dp_m2_n2 : &crtc_state->dp_m_n);
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}
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static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
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const struct intel_crtc_state *crtc_state,
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enum drrs_refresh_rate_type refresh_type)
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{
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struct intel_dp *intel_dp = dev_priv->drrs.dp;
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_display_mode *mode;
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if (!intel_dp) {
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drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
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return;
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}
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if (!crtc) {
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drm_dbg_kms(&dev_priv->drm,
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"DRRS: intel_crtc not initialized\n");
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return;
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}
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if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
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drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
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return;
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}
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if (refresh_type == dev_priv->drrs.refresh_rate_type)
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return;
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if (!crtc_state->hw.active) {
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drm_dbg_kms(&dev_priv->drm,
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"eDP encoder disabled. CRTC not Active\n");
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return;
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}
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if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv))
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intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type);
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else if (DISPLAY_VER(dev_priv) > 6)
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intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type);
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dev_priv->drrs.refresh_rate_type = refresh_type;
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if (refresh_type == DRRS_LOW_RR)
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mode = intel_dp->attached_connector->panel.downclock_mode;
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else
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mode = intel_dp->attached_connector->panel.fixed_mode;
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drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
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drm_mode_vrefresh(mode));
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}
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static void
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intel_drrs_enable_locked(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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dev_priv->drrs.busy_frontbuffer_bits = 0;
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dev_priv->drrs.dp = intel_dp;
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}
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/**
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* intel_drrs_enable - init drrs struct if supported
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* @intel_dp: DP struct
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* @crtc_state: A pointer to the active crtc state.
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*
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* Initializes frontbuffer_bits and drrs.dp
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*/
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void intel_drrs_enable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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if (!crtc_state->has_drrs)
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return;
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drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
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mutex_lock(&dev_priv->drrs.mutex);
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if (dev_priv->drrs.dp) {
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drm_warn(&dev_priv->drm, "DRRS already enabled\n");
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goto unlock;
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}
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intel_drrs_enable_locked(intel_dp);
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unlock:
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mutex_unlock(&dev_priv->drrs.mutex);
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}
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static void
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intel_drrs_disable_locked(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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intel_drrs_set_state(dev_priv, crtc_state, DRRS_HIGH_RR);
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dev_priv->drrs.dp = NULL;
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}
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/**
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* intel_drrs_disable - Disable DRRS
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* @intel_dp: DP struct
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* @old_crtc_state: Pointer to old crtc_state.
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*
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*/
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void intel_drrs_disable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *old_crtc_state)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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if (!old_crtc_state->has_drrs)
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return;
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mutex_lock(&dev_priv->drrs.mutex);
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if (!dev_priv->drrs.dp) {
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mutex_unlock(&dev_priv->drrs.mutex);
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return;
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}
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intel_drrs_disable_locked(intel_dp, old_crtc_state);
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mutex_unlock(&dev_priv->drrs.mutex);
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cancel_delayed_work_sync(&dev_priv->drrs.work);
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}
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/**
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* intel_drrs_update - Update DRRS state
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* @intel_dp: Intel DP
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* @crtc_state: new CRTC state
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*
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* This function will update DRRS states, disabling or enabling DRRS when
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* executing fastsets. For full modeset, intel_drrs_disable() and
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* intel_drrs_enable() should be called instead.
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*/
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void
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intel_drrs_update(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
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return;
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mutex_lock(&dev_priv->drrs.mutex);
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/* New state matches current one? */
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if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
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goto unlock;
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if (crtc_state->has_drrs)
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intel_drrs_enable_locked(intel_dp);
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else
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intel_drrs_disable_locked(intel_dp, crtc_state);
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unlock:
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mutex_unlock(&dev_priv->drrs.mutex);
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}
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static void intel_drrs_downclock_work(struct work_struct *work)
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{
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struct drm_i915_private *dev_priv =
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container_of(work, typeof(*dev_priv), drrs.work.work);
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struct intel_dp *intel_dp;
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struct drm_crtc *crtc;
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mutex_lock(&dev_priv->drrs.mutex);
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intel_dp = dev_priv->drrs.dp;
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if (!intel_dp)
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goto unlock;
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/*
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* The delayed work can race with an invalidate hence we need to
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* recheck.
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*/
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if (dev_priv->drrs.busy_frontbuffer_bits)
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goto unlock;
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crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
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intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config, DRRS_LOW_RR);
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unlock:
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mutex_unlock(&dev_priv->drrs.mutex);
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}
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static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv,
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unsigned int frontbuffer_bits,
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bool invalidate)
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{
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struct intel_dp *intel_dp;
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struct drm_crtc *crtc;
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enum pipe pipe;
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if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
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return;
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cancel_delayed_work(&dev_priv->drrs.work);
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mutex_lock(&dev_priv->drrs.mutex);
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intel_dp = dev_priv->drrs.dp;
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if (!intel_dp) {
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mutex_unlock(&dev_priv->drrs.mutex);
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return;
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}
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crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
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pipe = to_intel_crtc(crtc)->pipe;
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frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
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if (invalidate)
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dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
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else
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dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
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/* flush/invalidate means busy screen hence upclock */
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if (frontbuffer_bits)
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intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config,
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DRRS_HIGH_RR);
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/*
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* flush also means no more activity hence schedule downclock, if all
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* other fbs are quiescent too
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*/
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if (!invalidate && !dev_priv->drrs.busy_frontbuffer_bits)
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schedule_delayed_work(&dev_priv->drrs.work,
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msecs_to_jiffies(1000));
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mutex_unlock(&dev_priv->drrs.mutex);
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}
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/**
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* intel_drrs_invalidate - Disable Idleness DRRS
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* @dev_priv: i915 device
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* @frontbuffer_bits: frontbuffer plane tracking bits
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*
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* This function gets called everytime rendering on the given planes start.
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* Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
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*
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* Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
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*/
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void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
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unsigned int frontbuffer_bits)
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{
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intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true);
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}
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/**
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* intel_drrs_flush - Restart Idleness DRRS
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* @dev_priv: i915 device
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* @frontbuffer_bits: frontbuffer plane tracking bits
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*
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* This function gets called every time rendering on the given planes has
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* completed or flip on a crtc is completed. So DRRS should be upclocked
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* (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
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* if no other planes are dirty.
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*
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* Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
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*/
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void intel_drrs_flush(struct drm_i915_private *dev_priv,
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unsigned int frontbuffer_bits)
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{
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intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false);
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}
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void intel_drrs_page_flip(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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unsigned int frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
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intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false);
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}
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/**
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* intel_drrs_init - Init basic DRRS work and mutex.
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* @connector: eDP connector
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* @fixed_mode: preferred mode of panel
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*
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* This function is called only once at driver load to initialize basic
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* DRRS stuff.
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*
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* Returns:
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* Downclock mode if panel supports it, else return NULL.
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* DRRS support is determined by the presence of downclock mode (apart
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* from VBT setting).
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*/
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struct drm_display_mode *
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intel_drrs_init(struct intel_connector *connector,
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struct drm_display_mode *fixed_mode)
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{
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struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
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struct intel_encoder *encoder = connector->encoder;
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struct drm_display_mode *downclock_mode = NULL;
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INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_drrs_downclock_work);
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mutex_init(&dev_priv->drrs.mutex);
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if (DISPLAY_VER(dev_priv) <= 6) {
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drm_dbg_kms(&dev_priv->drm,
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"DRRS supported for Gen7 and above\n");
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return NULL;
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}
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if ((DISPLAY_VER(dev_priv) < 8 && !HAS_GMCH(dev_priv)) &&
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encoder->port != PORT_A) {
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drm_dbg_kms(&dev_priv->drm,
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"DRRS only supported on eDP port A\n");
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return NULL;
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}
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if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
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drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
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return NULL;
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}
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downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
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if (!downclock_mode) {
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drm_dbg_kms(&dev_priv->drm,
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"Downclock mode is not found. DRRS not supported\n");
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return NULL;
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}
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dev_priv->drrs.type = dev_priv->vbt.drrs_type;
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dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
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drm_dbg_kms(&dev_priv->drm,
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"seamless DRRS supported for eDP panel.\n");
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return downclock_mode;
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}
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