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24f90d6688
Clean up the SPDX licence declarations to comply with checkpatch. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-1-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2016 Intel Corporation
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*/
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#ifndef __INTEL_GGTT_FENCING_H__
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#define __INTEL_GGTT_FENCING_H__
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#include <linux/list.h>
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#include <linux/types.h>
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#include "i915_active.h"
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struct drm_i915_gem_object;
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struct i915_ggtt;
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struct i915_vma;
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struct intel_gt;
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struct sg_table;
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#define I965_FENCE_PAGE 4096UL
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struct i915_fence_reg {
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struct list_head link;
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struct i915_ggtt *ggtt;
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struct i915_vma *vma;
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atomic_t pin_count;
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struct i915_active active;
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int id;
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/**
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* Whether the tiling parameters for the currently
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* associated fence register have changed. Note that
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* for the purposes of tracking tiling changes we also
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* treat the unfenced register, the register slot that
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* the object occupies whilst it executes a fenced
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* command (such as BLT on gen2/3), as a "fence".
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*/
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bool dirty;
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u32 start;
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u32 size;
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u32 tiling;
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u32 stride;
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};
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struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt);
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void i915_unreserve_fence(struct i915_fence_reg *fence);
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void intel_ggtt_restore_fences(struct i915_ggtt *ggtt);
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void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
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struct sg_table *pages);
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void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
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struct sg_table *pages);
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void intel_ggtt_init_fences(struct i915_ggtt *ggtt);
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void intel_ggtt_fini_fences(struct i915_ggtt *ggtt);
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void intel_gt_init_swizzling(struct intel_gt *gt);
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#endif
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