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![Jani Nikula](/assets/img/avatar_default.png)
This is far from ideal, but it reduces the i915_drv.h dependency from intel_display_types.h. Maybe in the future we'll need a better split. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c6c60d9a8f6dcd1fa2f4b187000c5bb6843a1371.1638366969.git.jani.nikula@intel.com
76 lines
1.3 KiB
C
76 lines
1.3 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#ifndef __INTEL_PM_TYPES_H__
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#define __INTEL_PM_TYPES_H__
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#include <linux/types.h>
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#include "display/intel_display.h"
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enum intel_ddb_partitioning {
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INTEL_DDB_PART_1_2,
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INTEL_DDB_PART_5_6, /* IVB+ */
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};
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struct ilk_wm_values {
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u32 wm_pipe[3];
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u32 wm_lp[3];
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u32 wm_lp_spr[3];
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bool enable_fbc_wm;
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enum intel_ddb_partitioning partitioning;
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};
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struct g4x_pipe_wm {
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u16 plane[I915_MAX_PLANES];
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u16 fbc;
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};
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struct g4x_sr_wm {
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u16 plane;
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u16 cursor;
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u16 fbc;
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};
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struct vlv_wm_ddl_values {
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u8 plane[I915_MAX_PLANES];
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};
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struct vlv_wm_values {
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struct g4x_pipe_wm pipe[3];
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struct g4x_sr_wm sr;
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struct vlv_wm_ddl_values ddl[3];
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u8 level;
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bool cxsr;
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};
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struct g4x_wm_values {
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struct g4x_pipe_wm pipe[2];
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struct g4x_sr_wm sr;
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struct g4x_sr_wm hpll;
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bool cxsr;
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bool hpll_en;
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bool fbc_en;
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};
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struct skl_ddb_entry {
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u16 start, end; /* in number of blocks, 'end' is exclusive */
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};
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static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
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{
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return entry->end - entry->start;
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}
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static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
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const struct skl_ddb_entry *e2)
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{
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if (e1->start == e2->start && e1->end == e2->end)
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return true;
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return false;
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}
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#endif /* __INTEL_PM_TYPES_H__ */
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