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![Thierry Reding](/assets/img/avatar_default.png)
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
233 lines
5.5 KiB
C
233 lines
5.5 KiB
C
/*
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* Broadcom specific AMBA
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* GPIO driver
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*
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* Copyright 2011, Broadcom Corporation
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* Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/export.h>
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#include <linux/bcma/bcma.h>
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#include "bcma_private.h"
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#define BCMA_GPIO_MAX_PINS 32
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static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcma_drv_cc *cc = gpiochip_get_data(chip);
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return !!bcma_chipco_gpio_in(cc, 1 << gpio);
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}
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static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
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int value)
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{
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struct bcma_drv_cc *cc = gpiochip_get_data(chip);
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bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
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}
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static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcma_drv_cc *cc = gpiochip_get_data(chip);
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bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
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return 0;
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}
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static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
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int value)
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{
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struct bcma_drv_cc *cc = gpiochip_get_data(chip);
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bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
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bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
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return 0;
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}
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static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcma_drv_cc *cc = gpiochip_get_data(chip);
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bcma_chipco_gpio_control(cc, 1 << gpio, 0);
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/* clear pulldown */
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bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
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/* Set pullup */
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bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
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return 0;
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}
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static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcma_drv_cc *cc = gpiochip_get_data(chip);
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/* clear pullup */
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bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
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}
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#if IS_BUILTIN(CONFIG_BCM47XX) || IS_BUILTIN(CONFIG_ARCH_BCM_5301X)
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static void bcma_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct bcma_drv_cc *cc = gpiochip_get_data(gc);
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int gpio = irqd_to_hwirq(d);
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u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
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bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
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bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
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}
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static void bcma_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct bcma_drv_cc *cc = gpiochip_get_data(gc);
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int gpio = irqd_to_hwirq(d);
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bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
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}
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static struct irq_chip bcma_gpio_irq_chip = {
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.name = "BCMA-GPIO",
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.irq_mask = bcma_gpio_irq_mask,
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.irq_unmask = bcma_gpio_irq_unmask,
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};
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static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
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{
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struct bcma_drv_cc *cc = dev_id;
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struct gpio_chip *gc = &cc->gpio;
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u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
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u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
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u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
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unsigned long irqs = (val ^ pol) & mask;
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int gpio;
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if (!irqs)
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return IRQ_NONE;
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for_each_set_bit(gpio, &irqs, gc->ngpio)
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generic_handle_irq(irq_find_mapping(gc->irq.domain, gpio));
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bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
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return IRQ_HANDLED;
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}
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static int bcma_gpio_irq_init(struct bcma_drv_cc *cc)
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{
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struct gpio_chip *chip = &cc->gpio;
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int hwirq, err;
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if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
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return 0;
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hwirq = bcma_core_irq(cc->core, 0);
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err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
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cc);
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if (err)
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return err;
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bcma_chipco_gpio_intmask(cc, ~0, 0);
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bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
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err = gpiochip_irqchip_add(chip,
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&bcma_gpio_irq_chip,
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0,
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handle_simple_irq,
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IRQ_TYPE_NONE);
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if (err) {
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free_irq(hwirq, cc);
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return err;
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}
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return 0;
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}
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static void bcma_gpio_irq_exit(struct bcma_drv_cc *cc)
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{
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if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
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return;
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bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
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free_irq(bcma_core_irq(cc->core, 0), cc);
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}
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#else
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static int bcma_gpio_irq_init(struct bcma_drv_cc *cc)
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{
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return 0;
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}
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static void bcma_gpio_irq_exit(struct bcma_drv_cc *cc)
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{
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}
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#endif
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int bcma_gpio_init(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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struct gpio_chip *chip = &cc->gpio;
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int err;
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chip->label = "bcma_gpio";
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chip->owner = THIS_MODULE;
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chip->request = bcma_gpio_request;
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chip->free = bcma_gpio_free;
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chip->get = bcma_gpio_get_value;
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chip->set = bcma_gpio_set_value;
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chip->direction_input = bcma_gpio_direction_input;
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chip->direction_output = bcma_gpio_direction_output;
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chip->owner = THIS_MODULE;
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chip->parent = bcma_bus_get_host_dev(bus);
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#if IS_BUILTIN(CONFIG_OF)
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chip->of_node = cc->core->dev.of_node;
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#endif
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM4707:
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case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM53572:
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case BCMA_CHIP_ID_BCM53573:
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case BCMA_CHIP_ID_BCM47094:
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chip->ngpio = 32;
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break;
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default:
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chip->ngpio = 16;
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}
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/*
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* Register SoC GPIO devices with absolute GPIO pin base.
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* On MIPS, we don't have Device Tree and we can't use relative (per chip)
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* GPIO numbers.
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* On some ARM devices, user space may want to access some system GPIO
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* pins directly, which is easier to do with a predictable GPIO base.
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*/
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if (IS_BUILTIN(CONFIG_BCM47XX) ||
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cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
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chip->base = bus->num * BCMA_GPIO_MAX_PINS;
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else
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chip->base = -1;
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err = gpiochip_add_data(chip, cc);
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if (err)
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return err;
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err = bcma_gpio_irq_init(cc);
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if (err) {
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gpiochip_remove(chip);
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return err;
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}
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return 0;
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}
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int bcma_gpio_unregister(struct bcma_drv_cc *cc)
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{
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bcma_gpio_irq_exit(cc);
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gpiochip_remove(&cc->gpio);
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return 0;
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}
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