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![Borislav Petkov](/assets/img/avatar_default.png)
It is a write-only variable so get rid of it. Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Robert Richter <rric@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Thor Thayer <thor.thayer@linux.intel.com> Acked-by: Tony Luck <tony.luck@intel.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Jason Baron <jbaron@akamai.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Loc Ho <lho@apm.com> Cc: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org
283 lines
7.4 KiB
C
283 lines
7.4 KiB
C
/*
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* Copyright 2011-2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/edac.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <linux/uaccess.h>
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#include "edac_module.h"
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/* DDR Ctrlr Error Registers */
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#define HB_DDR_ECC_ERR_BASE 0x128
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#define MW_DDR_ECC_ERR_BASE 0x1b4
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#define HB_DDR_ECC_OPT 0x00
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#define HB_DDR_ECC_U_ERR_ADDR 0x08
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#define HB_DDR_ECC_U_ERR_STAT 0x0c
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#define HB_DDR_ECC_U_ERR_DATAL 0x10
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#define HB_DDR_ECC_U_ERR_DATAH 0x14
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#define HB_DDR_ECC_C_ERR_ADDR 0x18
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#define HB_DDR_ECC_C_ERR_STAT 0x1c
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#define HB_DDR_ECC_C_ERR_DATAL 0x20
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#define HB_DDR_ECC_C_ERR_DATAH 0x24
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#define HB_DDR_ECC_OPT_MODE_MASK 0x3
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#define HB_DDR_ECC_OPT_FWC 0x100
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#define HB_DDR_ECC_OPT_XOR_SHIFT 16
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/* DDR Ctrlr Interrupt Registers */
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#define HB_DDR_ECC_INT_BASE 0x180
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#define MW_DDR_ECC_INT_BASE 0x218
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#define HB_DDR_ECC_INT_STATUS 0x00
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#define HB_DDR_ECC_INT_ACK 0x04
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#define HB_DDR_ECC_INT_STAT_CE 0x8
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#define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10
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#define HB_DDR_ECC_INT_STAT_UE 0x20
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#define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40
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struct hb_mc_drvdata {
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void __iomem *mc_err_base;
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void __iomem *mc_int_base;
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};
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static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
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{
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struct mem_ctl_info *mci = dev_id;
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struct hb_mc_drvdata *drvdata = mci->pvt_info;
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u32 status, err_addr;
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/* Read the interrupt status register */
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status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
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if (status & HB_DDR_ECC_INT_STAT_UE) {
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err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
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err_addr >> PAGE_SHIFT,
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err_addr & ~PAGE_MASK, 0,
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0, 0, -1,
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mci->ctl_name, "");
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}
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if (status & HB_DDR_ECC_INT_STAT_CE) {
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u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
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syndrome = (syndrome >> 8) & 0xff;
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err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
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err_addr >> PAGE_SHIFT,
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err_addr & ~PAGE_MASK, syndrome,
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0, 0, -1,
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mci->ctl_name, "");
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}
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/* clear the error, clears the interrupt */
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writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
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return IRQ_HANDLED;
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}
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static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
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{
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struct hb_mc_drvdata *pdata = mci->pvt_info;
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u32 reg;
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reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
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reg &= HB_DDR_ECC_OPT_MODE_MASK;
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reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
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writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
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}
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#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
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static ssize_t highbank_mc_inject_ctrl(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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u8 synd;
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if (kstrtou8(buf, 16, &synd))
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return -EINVAL;
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highbank_mc_err_inject(mci, synd);
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return count;
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}
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static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);
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static struct attribute *highbank_dev_attrs[] = {
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&dev_attr_inject_ctrl.attr,
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NULL
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};
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ATTRIBUTE_GROUPS(highbank_dev);
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struct hb_mc_settings {
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int err_offset;
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int int_offset;
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};
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static struct hb_mc_settings hb_settings = {
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.err_offset = HB_DDR_ECC_ERR_BASE,
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.int_offset = HB_DDR_ECC_INT_BASE,
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};
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static struct hb_mc_settings mw_settings = {
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.err_offset = MW_DDR_ECC_ERR_BASE,
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.int_offset = MW_DDR_ECC_INT_BASE,
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};
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static const struct of_device_id hb_ddr_ctrl_of_match[] = {
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{ .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
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{ .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
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{},
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};
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MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
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static int highbank_mc_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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const struct hb_mc_settings *settings;
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struct edac_mc_layer layers[2];
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struct mem_ctl_info *mci;
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struct hb_mc_drvdata *drvdata;
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struct dimm_info *dimm;
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struct resource *r;
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void __iomem *base;
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u32 control;
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int irq;
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int res = 0;
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id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
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if (!id)
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return -ENODEV;
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = 1;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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layers[1].size = 1;
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layers[1].is_virt_csrow = false;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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sizeof(struct hb_mc_drvdata));
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if (!mci)
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return -ENOMEM;
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mci->pdev = &pdev->dev;
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drvdata = mci->pvt_info;
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platform_set_drvdata(pdev, mci);
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if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "Unable to get mem resource\n");
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res = -ENODEV;
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goto err;
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}
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if (!devm_request_mem_region(&pdev->dev, r->start,
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resource_size(r), dev_name(&pdev->dev))) {
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dev_err(&pdev->dev, "Error while requesting mem region\n");
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res = -EBUSY;
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goto err;
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}
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base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
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if (!base) {
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dev_err(&pdev->dev, "Unable to map regs\n");
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res = -ENOMEM;
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goto err;
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}
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settings = id->data;
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drvdata->mc_err_base = base + settings->err_offset;
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drvdata->mc_int_base = base + settings->int_offset;
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control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
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if (!control || (control == 0x2)) {
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dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
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res = -ENODEV;
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goto err;
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}
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mci->mtype_cap = MEM_FLAG_DDR3;
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
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mci->edac_cap = EDAC_FLAG_SECDED;
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mci->mod_name = pdev->dev.driver->name;
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mci->ctl_name = id->compatible;
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mci->dev_name = dev_name(&pdev->dev);
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mci->scrub_mode = SCRUB_SW_SRC;
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/* Only a single 4GB DIMM is supported */
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dimm = *mci->dimms;
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dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
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dimm->grain = 8;
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dimm->dtype = DEV_X8;
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dimm->mtype = MEM_DDR3;
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dimm->edac_mode = EDAC_SECDED;
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res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups);
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if (res < 0)
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goto err;
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irq = platform_get_irq(pdev, 0);
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res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
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0, dev_name(&pdev->dev), mci);
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if (res < 0) {
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dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
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goto err2;
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}
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devres_close_group(&pdev->dev, NULL);
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return 0;
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err2:
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edac_mc_del_mc(&pdev->dev);
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err:
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devres_release_group(&pdev->dev, NULL);
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edac_mc_free(mci);
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return res;
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}
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static int highbank_mc_remove(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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edac_mc_del_mc(&pdev->dev);
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edac_mc_free(mci);
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return 0;
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}
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static struct platform_driver highbank_mc_edac_driver = {
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.probe = highbank_mc_probe,
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.remove = highbank_mc_remove,
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.driver = {
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.name = "hb_mc_edac",
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.of_match_table = hb_ddr_ctrl_of_match,
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},
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};
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module_platform_driver(highbank_mc_edac_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Calxeda, Inc.");
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MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");
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