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![Pedro H. Penna](/assets/img/avatar_default.png)
Usually, hardware implicitly acknowledges interrupts when reading them. However, if this is not the case, the IRQ gets fired over and over again in the current implementation. This patch uses the right mask acknowledge function to handle the aforementioned situation on or1k processors that interact with such kind of hardware. Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Pedro H. Penna <pedrohenriquepenna@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
181 lines
4.6 KiB
C
181 lines
4.6 KiB
C
/*
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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* Copyright (C) 2014 Stefan Kristansson <stefan.kristiansson@saunalahti.fi>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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/* OR1K PIC implementation */
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struct or1k_pic_dev {
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struct irq_chip chip;
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irq_flow_handler_t handle;
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unsigned long flags;
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};
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/*
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* We're a couple of cycles faster than the generic implementations with
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* these 'fast' versions.
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*/
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static void or1k_pic_mask(struct irq_data *data)
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{
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
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}
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static void or1k_pic_unmask(struct irq_data *data)
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{
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));
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}
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static void or1k_pic_ack(struct irq_data *data)
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{
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mtspr(SPR_PICSR, (1UL << data->hwirq));
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}
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static void or1k_pic_mask_ack(struct irq_data *data)
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{
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
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mtspr(SPR_PICSR, (1UL << data->hwirq));
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}
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/*
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* There are two oddities with the OR1200 PIC implementation:
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* i) LEVEL-triggered interrupts are latched and need to be cleared
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* ii) the interrupt latch is cleared by writing a 0 to the bit,
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* as opposed to a 1 as mandated by the spec
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*/
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static void or1k_pic_or1200_ack(struct irq_data *data)
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{
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mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
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}
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static void or1k_pic_or1200_mask_ack(struct irq_data *data)
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{
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
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mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
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}
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static struct or1k_pic_dev or1k_pic_level = {
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.chip = {
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.name = "or1k-PIC-level",
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.irq_unmask = or1k_pic_unmask,
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.irq_mask = or1k_pic_mask,
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.irq_mask_ack = or1k_pic_mask_ack,
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},
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.handle = handle_level_irq,
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.flags = IRQ_LEVEL | IRQ_NOPROBE,
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};
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static struct or1k_pic_dev or1k_pic_edge = {
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.chip = {
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.name = "or1k-PIC-edge",
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.irq_unmask = or1k_pic_unmask,
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.irq_mask = or1k_pic_mask,
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.irq_ack = or1k_pic_ack,
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.irq_mask_ack = or1k_pic_mask_ack,
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},
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.handle = handle_edge_irq,
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.flags = IRQ_LEVEL | IRQ_NOPROBE,
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};
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static struct or1k_pic_dev or1k_pic_or1200 = {
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.chip = {
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.name = "or1200-PIC",
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.irq_unmask = or1k_pic_unmask,
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.irq_mask = or1k_pic_mask,
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.irq_ack = or1k_pic_or1200_ack,
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.irq_mask_ack = or1k_pic_or1200_mask_ack,
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},
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.handle = handle_level_irq,
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.flags = IRQ_LEVEL | IRQ_NOPROBE,
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};
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static struct irq_domain *root_domain;
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static inline int pic_get_irq(int first)
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{
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int hwirq;
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hwirq = ffs(mfspr(SPR_PICSR) >> first);
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if (!hwirq)
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return NO_IRQ;
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else
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hwirq = hwirq + first - 1;
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return hwirq;
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}
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static void or1k_pic_handle_irq(struct pt_regs *regs)
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{
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int irq = -1;
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while ((irq = pic_get_irq(irq + 1)) != NO_IRQ)
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handle_domain_irq(root_domain, irq, regs);
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}
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static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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struct or1k_pic_dev *pic = d->host_data;
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irq_set_chip_and_handler(irq, &pic->chip, pic->handle);
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irq_set_status_flags(irq, pic->flags);
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return 0;
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}
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static const struct irq_domain_ops or1k_irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = or1k_map,
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};
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/*
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* This sets up the IRQ domain for the PIC built in to the OpenRISC
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* 1000 CPU. This is the "root" domain as these are the interrupts
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* that directly trigger an exception in the CPU.
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*/
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static int __init or1k_pic_init(struct device_node *node,
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struct or1k_pic_dev *pic)
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{
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/* Disable all interrupts until explicitly requested */
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mtspr(SPR_PICMR, (0UL));
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root_domain = irq_domain_add_linear(node, 32, &or1k_irq_domain_ops,
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pic);
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set_handle_irq(or1k_pic_handle_irq);
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return 0;
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}
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static int __init or1k_pic_or1200_init(struct device_node *node,
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struct device_node *parent)
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{
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return or1k_pic_init(node, &or1k_pic_or1200);
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}
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IRQCHIP_DECLARE(or1k_pic_or1200, "opencores,or1200-pic", or1k_pic_or1200_init);
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IRQCHIP_DECLARE(or1k_pic, "opencores,or1k-pic", or1k_pic_or1200_init);
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static int __init or1k_pic_level_init(struct device_node *node,
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struct device_node *parent)
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{
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return or1k_pic_init(node, &or1k_pic_level);
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}
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IRQCHIP_DECLARE(or1k_pic_level, "opencores,or1k-pic-level",
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or1k_pic_level_init);
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static int __init or1k_pic_edge_init(struct device_node *node,
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struct device_node *parent)
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{
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return or1k_pic_init(node, &or1k_pic_edge);
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}
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IRQCHIP_DECLARE(or1k_pic_edge, "opencores,or1k-pic-edge", or1k_pic_edge_init);
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