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![Keith Busch](/assets/img/avatar_default.png)
The PCI bus config accessors could be inlined into other accessor functions, which makes it so they can't be traced. Force them to never be inlined so that ftrace can hook into these functions. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
590 lines
15 KiB
C
590 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/ioport.h>
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#include <linux/wait.h>
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#include "pci.h"
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/*
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* This interrupt-safe spinlock protects all accesses to PCI
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* configuration space.
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*/
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DEFINE_RAW_SPINLOCK(pci_lock);
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/*
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* Wrappers for all PCI configuration access functions. They just check
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* alignment, do locking and call the low-level functions pointed to
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* by pci_dev->ops.
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*/
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#define PCI_byte_BAD 0
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#define PCI_word_BAD (pos & 1)
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#define PCI_dword_BAD (pos & 3)
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#ifdef CONFIG_PCI_LOCKLESS_CONFIG
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# define pci_lock_config(f) do { (void)(f); } while (0)
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# define pci_unlock_config(f) do { (void)(f); } while (0)
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#else
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# define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
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# define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
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#endif
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#define PCI_OP_READ(size, type, len) \
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int noinline pci_bus_read_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
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{ \
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int res; \
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unsigned long flags; \
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u32 data = 0; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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pci_lock_config(flags); \
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res = bus->ops->read(bus, devfn, pos, len, &data); \
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*value = (type)data; \
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pci_unlock_config(flags); \
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return res; \
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}
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#define PCI_OP_WRITE(size, type, len) \
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int noinline pci_bus_write_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
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{ \
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int res; \
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unsigned long flags; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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pci_lock_config(flags); \
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res = bus->ops->write(bus, devfn, pos, len, value); \
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pci_unlock_config(flags); \
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return res; \
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}
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PCI_OP_READ(byte, u8, 1)
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PCI_OP_READ(word, u16, 2)
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PCI_OP_READ(dword, u32, 4)
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PCI_OP_WRITE(byte, u8, 1)
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PCI_OP_WRITE(word, u16, 2)
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PCI_OP_WRITE(dword, u32, 4)
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EXPORT_SYMBOL(pci_bus_read_config_byte);
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EXPORT_SYMBOL(pci_bus_read_config_word);
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EXPORT_SYMBOL(pci_bus_read_config_dword);
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EXPORT_SYMBOL(pci_bus_write_config_byte);
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EXPORT_SYMBOL(pci_bus_write_config_word);
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EXPORT_SYMBOL(pci_bus_write_config_dword);
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int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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void __iomem *addr;
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addr = bus->ops->map_bus(bus, devfn, where);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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if (size == 1)
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*val = readb(addr);
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else if (size == 2)
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*val = readw(addr);
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else
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*val = readl(addr);
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return PCIBIOS_SUCCESSFUL;
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}
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EXPORT_SYMBOL_GPL(pci_generic_config_read);
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int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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void __iomem *addr;
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addr = bus->ops->map_bus(bus, devfn, where);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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writeb(val, addr);
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else if (size == 2)
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writew(val, addr);
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else
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writel(val, addr);
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return PCIBIOS_SUCCESSFUL;
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}
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EXPORT_SYMBOL_GPL(pci_generic_config_write);
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int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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void __iomem *addr;
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addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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*val = readl(addr);
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if (size <= 2)
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*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
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return PCIBIOS_SUCCESSFUL;
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}
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EXPORT_SYMBOL_GPL(pci_generic_config_read32);
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int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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void __iomem *addr;
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u32 mask, tmp;
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addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 4) {
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writel(val, addr);
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* In general, hardware that supports only 32-bit writes on PCI is
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* not spec-compliant. For example, software may perform a 16-bit
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* write. If the hardware only supports 32-bit accesses, we must
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* do a 32-bit read, merge in the 16 bits we intend to write,
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* followed by a 32-bit write. If the 16 bits we *don't* intend to
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* write happen to have any RW1C (write-one-to-clear) bits set, we
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* just inadvertently cleared something we shouldn't have.
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*/
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dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
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size, pci_domain_nr(bus), bus->number,
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PCI_SLOT(devfn), PCI_FUNC(devfn), where);
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mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
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tmp = readl(addr) & mask;
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tmp |= val << ((where & 0x3) * 8);
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writel(tmp, addr);
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return PCIBIOS_SUCCESSFUL;
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}
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EXPORT_SYMBOL_GPL(pci_generic_config_write32);
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/**
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* pci_bus_set_ops - Set raw operations of pci bus
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* @bus: pci bus struct
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* @ops: new raw operations
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*
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* Return previous raw operations
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*/
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struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
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{
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struct pci_ops *old_ops;
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unsigned long flags;
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raw_spin_lock_irqsave(&pci_lock, flags);
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old_ops = bus->ops;
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bus->ops = ops;
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raw_spin_unlock_irqrestore(&pci_lock, flags);
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return old_ops;
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}
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EXPORT_SYMBOL(pci_bus_set_ops);
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/*
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* The following routines are to prevent the user from accessing PCI config
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* space when it's unsafe to do so. Some devices require this during BIST and
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* we're required to prevent it during D-state transitions.
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*
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* We have a bit per device to indicate it's blocked and a global wait queue
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* for callers to sleep on until devices are unblocked.
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*/
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static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
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static noinline void pci_wait_cfg(struct pci_dev *dev)
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{
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DECLARE_WAITQUEUE(wait, current);
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__add_wait_queue(&pci_cfg_wait, &wait);
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do {
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set_current_state(TASK_UNINTERRUPTIBLE);
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raw_spin_unlock_irq(&pci_lock);
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schedule();
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raw_spin_lock_irq(&pci_lock);
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} while (dev->block_cfg_access);
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__remove_wait_queue(&pci_cfg_wait, &wait);
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}
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/* Returns 0 on success, negative values indicate error. */
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#define PCI_USER_READ_CONFIG(size, type) \
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int pci_user_read_config_##size \
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(struct pci_dev *dev, int pos, type *val) \
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{ \
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int ret = PCIBIOS_SUCCESSFUL; \
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u32 data = -1; \
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if (PCI_##size##_BAD) \
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return -EINVAL; \
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raw_spin_lock_irq(&pci_lock); \
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if (unlikely(dev->block_cfg_access)) \
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pci_wait_cfg(dev); \
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ret = dev->bus->ops->read(dev->bus, dev->devfn, \
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pos, sizeof(type), &data); \
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raw_spin_unlock_irq(&pci_lock); \
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*val = (type)data; \
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return pcibios_err_to_errno(ret); \
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} \
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EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
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/* Returns 0 on success, negative values indicate error. */
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#define PCI_USER_WRITE_CONFIG(size, type) \
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int pci_user_write_config_##size \
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(struct pci_dev *dev, int pos, type val) \
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{ \
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int ret = PCIBIOS_SUCCESSFUL; \
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if (PCI_##size##_BAD) \
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return -EINVAL; \
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raw_spin_lock_irq(&pci_lock); \
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if (unlikely(dev->block_cfg_access)) \
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pci_wait_cfg(dev); \
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ret = dev->bus->ops->write(dev->bus, dev->devfn, \
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pos, sizeof(type), val); \
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raw_spin_unlock_irq(&pci_lock); \
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return pcibios_err_to_errno(ret); \
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} \
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EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
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PCI_USER_READ_CONFIG(byte, u8)
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PCI_USER_READ_CONFIG(word, u16)
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PCI_USER_READ_CONFIG(dword, u32)
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PCI_USER_WRITE_CONFIG(byte, u8)
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PCI_USER_WRITE_CONFIG(word, u16)
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PCI_USER_WRITE_CONFIG(dword, u32)
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/**
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* pci_cfg_access_lock - Lock PCI config reads/writes
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* @dev: pci device struct
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*
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* When access is locked, any userspace reads or writes to config
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* space and concurrent lock requests will sleep until access is
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* allowed via pci_cfg_access_unlock() again.
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*/
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void pci_cfg_access_lock(struct pci_dev *dev)
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{
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might_sleep();
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raw_spin_lock_irq(&pci_lock);
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if (dev->block_cfg_access)
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pci_wait_cfg(dev);
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dev->block_cfg_access = 1;
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raw_spin_unlock_irq(&pci_lock);
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}
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EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
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/**
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* pci_cfg_access_trylock - try to lock PCI config reads/writes
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* @dev: pci device struct
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*
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* Same as pci_cfg_access_lock, but will return 0 if access is
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* already locked, 1 otherwise. This function can be used from
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* atomic contexts.
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*/
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bool pci_cfg_access_trylock(struct pci_dev *dev)
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{
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unsigned long flags;
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bool locked = true;
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raw_spin_lock_irqsave(&pci_lock, flags);
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if (dev->block_cfg_access)
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locked = false;
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else
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dev->block_cfg_access = 1;
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raw_spin_unlock_irqrestore(&pci_lock, flags);
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return locked;
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}
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EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
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/**
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* pci_cfg_access_unlock - Unlock PCI config reads/writes
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* @dev: pci device struct
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*
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* This function allows PCI config accesses to resume.
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*/
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void pci_cfg_access_unlock(struct pci_dev *dev)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&pci_lock, flags);
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/*
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* This indicates a problem in the caller, but we don't need
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* to kill them, unlike a double-block above.
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*/
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WARN_ON(!dev->block_cfg_access);
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dev->block_cfg_access = 0;
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raw_spin_unlock_irqrestore(&pci_lock, flags);
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wake_up_all(&pci_cfg_wait);
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}
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EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
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static inline int pcie_cap_version(const struct pci_dev *dev)
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{
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return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
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}
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static bool pcie_downstream_port(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_DOWNSTREAM ||
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type == PCI_EXP_TYPE_PCIE_BRIDGE;
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}
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bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return type == PCI_EXP_TYPE_ENDPOINT ||
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type == PCI_EXP_TYPE_LEG_END ||
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type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_UPSTREAM ||
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type == PCI_EXP_TYPE_DOWNSTREAM ||
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type == PCI_EXP_TYPE_PCI_BRIDGE ||
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type == PCI_EXP_TYPE_PCIE_BRIDGE;
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}
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static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
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{
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return pcie_downstream_port(dev) &&
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pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
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}
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static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_RC_EC;
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}
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static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
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{
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if (!pci_is_pcie(dev))
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return false;
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switch (pos) {
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case PCI_EXP_FLAGS:
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return true;
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case PCI_EXP_DEVCAP:
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case PCI_EXP_DEVCTL:
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case PCI_EXP_DEVSTA:
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return true;
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case PCI_EXP_LNKCAP:
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case PCI_EXP_LNKCTL:
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case PCI_EXP_LNKSTA:
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return pcie_cap_has_lnkctl(dev);
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case PCI_EXP_SLTCAP:
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case PCI_EXP_SLTCTL:
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case PCI_EXP_SLTSTA:
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return pcie_cap_has_sltctl(dev);
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case PCI_EXP_RTCTL:
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case PCI_EXP_RTCAP:
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case PCI_EXP_RTSTA:
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return pcie_cap_has_rtctl(dev);
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case PCI_EXP_DEVCAP2:
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case PCI_EXP_DEVCTL2:
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case PCI_EXP_LNKCAP2:
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case PCI_EXP_LNKCTL2:
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case PCI_EXP_LNKSTA2:
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return pcie_cap_version(dev) > 1;
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default:
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return false;
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}
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}
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/*
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* Note that these accessor functions are only for the "PCI Express
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* Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
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* other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
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*/
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int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
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{
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int ret;
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*val = 0;
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if (pos & 1)
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return -EINVAL;
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if (pcie_capability_reg_implemented(dev, pos)) {
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ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
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/*
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* Reset *val to 0 if pci_read_config_word() fails, it may
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* have been written as 0xFFFF if hardware error happens
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* during pci_read_config_word().
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*/
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if (ret)
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*val = 0;
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return ret;
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}
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/*
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* For Functions that do not implement the Slot Capabilities,
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* Slot Status, and Slot Control registers, these spaces must
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* be hardwired to 0b, with the exception of the Presence Detect
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* State bit in the Slot Status register of Downstream Ports,
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* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
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*/
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if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
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pos == PCI_EXP_SLTSTA)
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*val = PCI_EXP_SLTSTA_PDS;
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return 0;
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}
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EXPORT_SYMBOL(pcie_capability_read_word);
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int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
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{
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int ret;
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*val = 0;
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if (pos & 3)
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return -EINVAL;
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if (pcie_capability_reg_implemented(dev, pos)) {
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ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
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/*
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* Reset *val to 0 if pci_read_config_dword() fails, it may
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* have been written as 0xFFFFFFFF if hardware error happens
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* during pci_read_config_dword().
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*/
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if (ret)
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*val = 0;
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return ret;
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}
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if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
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pos == PCI_EXP_SLTSTA)
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*val = PCI_EXP_SLTSTA_PDS;
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return 0;
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}
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EXPORT_SYMBOL(pcie_capability_read_dword);
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int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
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{
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if (pos & 1)
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return -EINVAL;
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if (!pcie_capability_reg_implemented(dev, pos))
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return 0;
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return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
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}
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EXPORT_SYMBOL(pcie_capability_write_word);
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int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
|
|
{
|
|
if (pos & 3)
|
|
return -EINVAL;
|
|
|
|
if (!pcie_capability_reg_implemented(dev, pos))
|
|
return 0;
|
|
|
|
return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_write_dword);
|
|
|
|
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
|
|
u16 clear, u16 set)
|
|
{
|
|
int ret;
|
|
u16 val;
|
|
|
|
ret = pcie_capability_read_word(dev, pos, &val);
|
|
if (!ret) {
|
|
val &= ~clear;
|
|
val |= set;
|
|
ret = pcie_capability_write_word(dev, pos, val);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
|
|
|
|
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
|
|
u32 clear, u32 set)
|
|
{
|
|
int ret;
|
|
u32 val;
|
|
|
|
ret = pcie_capability_read_dword(dev, pos, &val);
|
|
if (!ret) {
|
|
val &= ~clear;
|
|
val |= set;
|
|
ret = pcie_capability_write_dword(dev, pos, val);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
|
|
|
|
int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
|
|
{
|
|
if (pci_dev_is_disconnected(dev)) {
|
|
*val = ~0;
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
|
|
}
|
|
EXPORT_SYMBOL(pci_read_config_byte);
|
|
|
|
int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
|
|
{
|
|
if (pci_dev_is_disconnected(dev)) {
|
|
*val = ~0;
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
|
|
}
|
|
EXPORT_SYMBOL(pci_read_config_word);
|
|
|
|
int pci_read_config_dword(const struct pci_dev *dev, int where,
|
|
u32 *val)
|
|
{
|
|
if (pci_dev_is_disconnected(dev)) {
|
|
*val = ~0;
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
|
|
}
|
|
EXPORT_SYMBOL(pci_read_config_dword);
|
|
|
|
int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
|
|
{
|
|
if (pci_dev_is_disconnected(dev))
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
|
|
}
|
|
EXPORT_SYMBOL(pci_write_config_byte);
|
|
|
|
int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
|
|
{
|
|
if (pci_dev_is_disconnected(dev))
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
|
|
}
|
|
EXPORT_SYMBOL(pci_write_config_word);
|
|
|
|
int pci_write_config_dword(const struct pci_dev *dev, int where,
|
|
u32 val)
|
|
{
|
|
if (pci_dev_is_disconnected(dev))
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
|
|
}
|
|
EXPORT_SYMBOL(pci_write_config_dword);
|