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![Arvind Yadav](/assets/img/avatar_default.png)
Undo preparation of a clock source if vt8500_pwm_probe() is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
277 lines
6.8 KiB
C
277 lines
6.8 KiB
C
/*
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* drivers/pwm/pwm-vt8500.c
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*
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* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
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* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/pwm.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <asm/div64.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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/*
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* SoC architecture allocates register space for 4 PWMs but only
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* 2 are currently implemented.
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*/
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#define VT8500_NR_PWMS 2
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#define REG_CTRL(pwm) (((pwm) << 4) + 0x00)
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#define REG_SCALAR(pwm) (((pwm) << 4) + 0x04)
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#define REG_PERIOD(pwm) (((pwm) << 4) + 0x08)
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#define REG_DUTY(pwm) (((pwm) << 4) + 0x0C)
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#define REG_STATUS 0x40
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#define CTRL_ENABLE BIT(0)
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#define CTRL_INVERT BIT(1)
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#define CTRL_AUTOLOAD BIT(2)
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#define CTRL_STOP_IMM BIT(3)
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#define CTRL_LOAD_PRESCALE BIT(4)
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#define CTRL_LOAD_PERIOD BIT(5)
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#define STATUS_CTRL_UPDATE BIT(0)
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#define STATUS_SCALAR_UPDATE BIT(1)
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#define STATUS_PERIOD_UPDATE BIT(2)
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#define STATUS_DUTY_UPDATE BIT(3)
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#define STATUS_ALL_UPDATE 0x0F
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struct vt8500_chip {
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struct pwm_chip chip;
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void __iomem *base;
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struct clk *clk;
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};
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#define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip)
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#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
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static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
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{
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int loops = msecs_to_loops(10);
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u32 mask = bitmask << (nr << 8);
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while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
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cpu_relax();
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if (unlikely(!loops))
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dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
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mask);
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}
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static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
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unsigned long long c;
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unsigned long period_cycles, prescale, pv, dc;
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int err;
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u32 val;
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err = clk_enable(vt8500->clk);
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if (err < 0) {
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dev_err(chip->dev, "failed to enable clock\n");
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return err;
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}
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c = clk_get_rate(vt8500->clk);
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c = c * period_ns;
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do_div(c, 1000000000);
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period_cycles = c;
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if (period_cycles < 1)
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period_cycles = 1;
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prescale = (period_cycles - 1) / 4096;
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pv = period_cycles / (prescale + 1) - 1;
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if (pv > 4095)
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pv = 4095;
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if (prescale > 1023) {
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clk_disable(vt8500->clk);
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return -EINVAL;
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}
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c = (unsigned long long)pv * duty_ns;
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do_div(c, period_ns);
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dc = c;
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writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
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pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);
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writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
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pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);
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writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
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pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);
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val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
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val |= CTRL_AUTOLOAD;
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writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
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pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
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clk_disable(vt8500->clk);
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return 0;
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}
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static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
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int err;
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u32 val;
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err = clk_enable(vt8500->clk);
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if (err < 0) {
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dev_err(chip->dev, "failed to enable clock\n");
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return err;
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}
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val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
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val |= CTRL_ENABLE;
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writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
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pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
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return 0;
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}
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static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
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u32 val;
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val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
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val &= ~CTRL_ENABLE;
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writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
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pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
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clk_disable(vt8500->clk);
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}
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static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
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u32 val;
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val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
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if (polarity == PWM_POLARITY_INVERSED)
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val |= CTRL_INVERT;
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else
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val &= ~CTRL_INVERT;
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writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
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pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
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return 0;
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}
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static const struct pwm_ops vt8500_pwm_ops = {
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.enable = vt8500_pwm_enable,
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.disable = vt8500_pwm_disable,
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.config = vt8500_pwm_config,
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.set_polarity = vt8500_pwm_set_polarity,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id vt8500_pwm_dt_ids[] = {
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{ .compatible = "via,vt8500-pwm", },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);
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static int vt8500_pwm_probe(struct platform_device *pdev)
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{
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struct vt8500_chip *chip;
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struct resource *r;
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struct device_node *np = pdev->dev.of_node;
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int ret;
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if (!np) {
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dev_err(&pdev->dev, "invalid devicetree node\n");
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return -EINVAL;
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}
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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return -ENOMEM;
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chip->chip.dev = &pdev->dev;
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chip->chip.ops = &vt8500_pwm_ops;
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chip->chip.of_xlate = of_pwm_xlate_with_flags;
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chip->chip.of_pwm_n_cells = 3;
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chip->chip.base = -1;
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chip->chip.npwm = VT8500_NR_PWMS;
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chip->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(chip->clk)) {
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dev_err(&pdev->dev, "clock source not specified\n");
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return PTR_ERR(chip->clk);
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}
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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chip->base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(chip->base))
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return PTR_ERR(chip->base);
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ret = clk_prepare(chip->clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to prepare clock\n");
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return ret;
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}
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ret = pwmchip_add(&chip->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to add PWM chip\n");
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clk_unprepare(chip->clk);
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return ret;
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}
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platform_set_drvdata(pdev, chip);
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return ret;
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}
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static int vt8500_pwm_remove(struct platform_device *pdev)
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{
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struct vt8500_chip *chip;
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chip = platform_get_drvdata(pdev);
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if (chip == NULL)
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return -ENODEV;
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clk_unprepare(chip->clk);
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return pwmchip_remove(&chip->chip);
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}
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static struct platform_driver vt8500_pwm_driver = {
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.probe = vt8500_pwm_probe,
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.remove = vt8500_pwm_remove,
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.driver = {
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.name = "vt8500-pwm",
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.of_match_table = vt8500_pwm_dt_ids,
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},
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};
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module_platform_driver(vt8500_pwm_driver);
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MODULE_DESCRIPTION("VT8500 PWM Driver");
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MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
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MODULE_LICENSE("GPL v2");
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