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2507a3d982
The trace parameter initialisation code is repeated in two different places, something that bloats the file and can lead to errors. This is fixed by introducing a helper function and calling the right protocol initialisation code when required. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Suzuki K Poulouse <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20190212171618.25355-7-mathieu.poirier@linaro.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
132 lines
3.2 KiB
C
132 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright(C) 2015 Linaro Limited. All rights reserved.
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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*/
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#ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
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#define INCLUDE__UTIL_PERF_CS_ETM_H__
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#include "util/event.h"
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#include "util/session.h"
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/* Versionning header in case things need tro change in the future. That way
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* decoding of old snapshot is still possible.
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*/
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enum {
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/* Starting with 0x0 */
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CS_HEADER_VERSION_0,
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/* PMU->type (32 bit), total # of CPUs (32 bit) */
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CS_PMU_TYPE_CPUS,
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CS_ETM_SNAPSHOT,
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CS_HEADER_VERSION_0_MAX,
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};
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/* Beginning of header common to both ETMv3 and V4 */
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enum {
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CS_ETM_MAGIC,
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CS_ETM_CPU,
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};
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/* ETMv3/PTM metadata */
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enum {
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/* Dynamic, configurable parameters */
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CS_ETM_ETMCR = CS_ETM_CPU + 1,
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CS_ETM_ETMTRACEIDR,
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/* RO, taken from sysFS */
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CS_ETM_ETMCCER,
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CS_ETM_ETMIDR,
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CS_ETM_PRIV_MAX,
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};
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/* ETMv4 metadata */
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enum {
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/* Dynamic, configurable parameters */
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CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1,
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CS_ETMV4_TRCTRACEIDR,
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/* RO, taken from sysFS */
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CS_ETMV4_TRCIDR0,
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CS_ETMV4_TRCIDR1,
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CS_ETMV4_TRCIDR2,
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CS_ETMV4_TRCIDR8,
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CS_ETMV4_TRCAUTHSTATUS,
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CS_ETMV4_PRIV_MAX,
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};
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/*
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* ETMv3 exception encoding number:
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* See Embedded Trace Macrocell spcification (ARM IHI 0014Q)
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* table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
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*/
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enum {
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CS_ETMV3_EXC_NONE = 0,
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CS_ETMV3_EXC_DEBUG_HALT = 1,
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CS_ETMV3_EXC_SMC = 2,
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CS_ETMV3_EXC_HYP = 3,
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CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
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CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
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CS_ETMV3_EXC_PE_RESET = 8,
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CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
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CS_ETMV3_EXC_SVC = 10,
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CS_ETMV3_EXC_PREFETCH_ABORT = 11,
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CS_ETMV3_EXC_DATA_FAULT = 12,
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CS_ETMV3_EXC_GENERIC = 13,
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CS_ETMV3_EXC_IRQ = 14,
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CS_ETMV3_EXC_FIQ = 15,
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};
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/*
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* ETMv4 exception encoding number:
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* See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
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* table 6-12 Possible values for the TYPE field in an Exception instruction
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* trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
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*/
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enum {
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CS_ETMV4_EXC_RESET = 0,
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CS_ETMV4_EXC_DEBUG_HALT = 1,
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CS_ETMV4_EXC_CALL = 2,
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CS_ETMV4_EXC_TRAP = 3,
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CS_ETMV4_EXC_SYSTEM_ERROR = 4,
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CS_ETMV4_EXC_INST_DEBUG = 6,
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CS_ETMV4_EXC_DATA_DEBUG = 7,
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CS_ETMV4_EXC_ALIGNMENT = 10,
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CS_ETMV4_EXC_INST_FAULT = 11,
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CS_ETMV4_EXC_DATA_FAULT = 12,
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CS_ETMV4_EXC_IRQ = 14,
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CS_ETMV4_EXC_FIQ = 15,
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CS_ETMV4_EXC_END = 31,
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};
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/* RB tree for quick conversion between traceID and metadata pointers */
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struct intlist *traceid_list;
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#define KiB(x) ((x) * 1024)
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#define MiB(x) ((x) * 1024 * 1024)
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#define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64))
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#define __perf_cs_etmv3_magic 0x3030303030303030ULL
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#define __perf_cs_etmv4_magic 0x4040404040404040ULL
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#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
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#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
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#ifdef HAVE_CSTRACE_SUPPORT
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int cs_etm__process_auxtrace_info(union perf_event *event,
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struct perf_session *session);
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int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
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#else
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static inline int
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cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused,
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struct perf_session *session __maybe_unused)
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{
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return -1;
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}
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static inline int cs_etm__get_cpu(u8 trace_chan_id __maybe_unused,
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int *cpu __maybe_unused)
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{
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return -1;
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}
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#endif
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#endif
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