Vincent Chen 0935afc397 clk: sifive: allocate sufficient memory for struct __prci_data ... [ Upstream commit d0a5fdf4cc ] The (struct __prci_data).hw_clks.hws is an array with dynamic elements. Using struct_size(pd, hw_clks.hws, ARRAY_SIZE(__prci_init_clocks)) instead of sizeof(*pd) to get the correct memory size of struct __prci_data for sifive/fu540-prci. After applying this modifications, the kernel runs smoothly with CONFIG_SLAB_FREELIST_RANDOM enabled on the HiFive unleashed board. Fixes: 30b8e27e3b ("clk: sifive: add a driver for the SiFive FU540 PRCI IP block") Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2020-06-30 15:37:01 -04:00
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actions
analogbits
at91	clk: at91: usb: continue if clk_hw_round_rate() return zero	2020-04-23 10:36:28 +02:00
axis
axs10x
bcm	clk: bcm2835: Fix return type of bcm2835_register_gate	2020-06-24 17:50:34 +02:00
berlin
davinci
h8300
hisilicon
imgtec
imx	clk: imx: Align imx sc clock parent msg structs to 4	2020-04-02 15:11:02 +02:00
ingenic	clk: ingenic/TCU: Fix round_rate returning error	2020-04-17 10:50:21 +02:00
keystone
loongson1
mediatek	clk: mediatek: assign the initial value to clk_init_data of mtk_mux	2020-06-22 09:31:19 +02:00
meson	clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers	2020-06-24 17:50:23 +02:00
microchip
mmp	clk: mmp2: Fix the order of timer mux parents	2020-02-05 21:22:43 +00:00
mvebu
mxs
nxp
pistachio
pxa	clk: pxa: fix one of the pxa RTC clocks	2020-01-04 19:18:11 +01:00
qcom	clk: qcom: msm8916: Fix the address location of pll->config_reg	2020-06-24 17:50:09 +02:00
renesas	clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling	2020-06-24 17:50:14 +02:00
rockchip	clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocks	2020-05-20 08:20:35 +02:00
samsung	clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1	2020-06-24 17:50:30 +02:00
sifive	clk: sifive: allocate sufficient memory for struct __prci_data	2020-06-30 15:37:01 -04:00
sirf
socfpga
spear
sprd	clk: sprd: return correct type of value for _sprd_pll_recalc_rate	2020-06-24 17:50:35 +02:00
st	clk: clk-flexgen: fix clock-critical handling	2020-06-24 17:50:17 +02:00
sunxi	clk: sunxi: Fix incorrect usage of round_down()	2020-06-24 17:50:08 +02:00
sunxi-ng	clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock	2020-02-24 08:36:42 +01:00
tegra	clk: tegra: Fix Tegra PMC clock out parents	2020-04-23 10:36:29 +02:00
ti	clk: ti: composite: fix memory leak	2020-06-24 17:50:26 +02:00
uniphier	clk: uniphier: Add SCSSI clock gate for each channel	2020-02-24 08:36:42 +01:00
ux500
versatile
x86
zte
zynq
zynqmp	clk: zynqmp: fix memory leak in zynqmp_register_clocks	2020-06-24 17:50:16 +02:00
clk-asm9260.c
clk-aspeed.c
clk-aspeed.h
clk-ast2600.c	clk: ast2600: Fix AHB clock divider for A1	2020-06-24 17:50:35 +02:00
clk-axi-clkgen.c
clk-axm5516.c
clk-bd718x7.c
clk-bulk.c
clk-cdce706.c
clk-cdce925.c
clk-clps711x.c
clk-composite.c
clk-conf.c
clk-cs2000-cp.c
clk-devres.c
clk-divider.c
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-mmio.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-gate.c
clk-gemini.c
clk-gpio.c	clk: clk-gpio: propagate rate change to parent	2020-01-04 19:17:21 +01:00
clk-hi655x.c
clk-highbank.c
clk-hsdk-pll.c
clk-lochnagar.c
clk-max9485.c
clk-max77686.c
clk-milbeaut.c
clk-moxart.c
clk-multiplier.c
clk-mux.c
clk-nomadik.c
clk-npcm7xx.c
clk-nspire.c
clk-oxnas.c
clk-palmas.c
clk-pwm.c
clk-qoriq.c
clk-rk808.c
clk-s2mps11.c
clk-scmi.c
clk-scpi.c
clk-si514.c
clk-si544.c
clk-si570.c
clk-si5341.c
clk-si5351.c
clk-si5351.h
clk-stm32f4.c
clk-stm32h7.c
clk-stm32mp1.c
clk-tango4.c
clk-twl6040.c
clk-u300.c
clk-versaclock5.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c	PM: runtime: clk: Fix clk_pm_runtime_get() error path	2020-06-17 16:40:30 +02:00
clk.h
clkdev.c
Kconfig
Makefile