368 lines
11 KiB
C
368 lines
11 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022-2023 Intel Corporation
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*/
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#ifndef _XE_GT_TYPES_H_
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#define _XE_GT_TYPES_H_
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#include "xe_force_wake_types.h"
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#include "xe_gt_idle_types.h"
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#include "xe_hw_engine_types.h"
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#include "xe_hw_fence_types.h"
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#include "xe_reg_sr_types.h"
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#include "xe_sa_types.h"
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#include "xe_uc_types.h"
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struct xe_exec_queue_ops;
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struct xe_migrate;
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struct xe_ring_ops;
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enum xe_gt_type {
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XE_GT_TYPE_UNINITIALIZED,
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XE_GT_TYPE_MAIN,
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XE_GT_TYPE_MEDIA,
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};
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#define XE_MAX_DSS_FUSE_REGS 3
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#define XE_MAX_EU_FUSE_REGS 1
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typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(32 * XE_MAX_DSS_FUSE_REGS)];
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typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(32 * XE_MAX_EU_FUSE_REGS)];
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struct xe_mmio_range {
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u32 start;
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u32 end;
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};
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/*
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* The hardware has multiple kinds of multicast register ranges that need
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* special register steering (and future platforms are expected to add
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* additional types).
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*
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* During driver startup, we initialize the steering control register to
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* direct reads to a slice/subslice that are valid for the 'subslice' class
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* of multicast registers. If another type of steering does not have any
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* overlap in valid steering targets with 'subslice' style registers, we will
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* need to explicitly re-steer reads of registers of the other type.
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*
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* Only the replication types that may need additional non-default steering
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* are listed here.
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*/
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enum xe_steering_type {
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L3BANK,
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MSLICE,
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LNCF,
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DSS,
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OADDRM,
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SQIDI_PSMI,
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/*
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* On some platforms there are multiple types of MCR registers that
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* will always return a non-terminated value at instance (0, 0). We'll
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* lump those all into a single category to keep things simple.
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*/
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INSTANCE0,
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/*
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* Register ranges that don't need special steering for each register:
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* it's sufficient to keep the HW-default for the selector, or only
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* change it once, on GT initialization. This needs to be the last
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* steering type.
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*/
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IMPLICIT_STEERING,
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NUM_STEERING_TYPES
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};
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#define gt_to_tile(gt__) \
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_Generic(gt__, \
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const struct xe_gt * : (const struct xe_tile *)((gt__)->tile), \
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struct xe_gt * : (gt__)->tile)
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#define gt_to_xe(gt__) \
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_Generic(gt__, \
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const struct xe_gt * : (const struct xe_device *)(gt_to_tile(gt__)->xe), \
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struct xe_gt * : gt_to_tile(gt__)->xe)
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/**
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* struct xe_gt - A "Graphics Technology" unit of the GPU
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*
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* A GT ("Graphics Technology") is the subset of a GPU primarily responsible
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* for implementing the graphics, compute, and/or media IP. It encapsulates
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* the hardware engines, programmable execution units, and GuC. Each GT has
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* its own handling of power management (RC6+forcewake) and multicast register
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* steering.
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*
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* A GPU/tile may have a single GT that supplies all graphics, compute, and
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* media functionality, or the graphics/compute and media may be split into
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* separate GTs within a tile.
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*/
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struct xe_gt {
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/** @tile: Backpointer to GT's tile */
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struct xe_tile *tile;
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/** @info: GT info */
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struct {
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/** @info.type: type of GT */
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enum xe_gt_type type;
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/** @info.id: Unique ID of this GT within the PCI Device */
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u8 id;
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/** @info.reference_clock: clock frequency */
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u32 reference_clock;
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/** @info.engine_mask: mask of engines present on GT */
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u64 engine_mask;
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/**
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* @info.__engine_mask: mask of engines present on GT read from
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* xe_pci.c, used to fake reading the engine_mask from the
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* hwconfig blob.
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*/
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u64 __engine_mask;
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/** @info.gmdid: raw GMD_ID value from hardware */
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u32 gmdid;
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} info;
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/**
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* @mmio: mmio info for GT. All GTs within a tile share the same
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* register space, but have their own copy of GSI registers at a
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* specific offset, as well as their own forcewake handling.
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*/
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struct {
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/** @mmio.fw: force wake for GT */
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struct xe_force_wake fw;
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/**
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* @mmio.adj_limit: adjust MMIO address if address is below this
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* value
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*/
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u32 adj_limit;
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/** @mmio.adj_offset: offect to add to MMIO address when adjusting */
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u32 adj_offset;
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} mmio;
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/**
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* @reg_sr: table with registers to be restored on GT init/resume/reset
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*/
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struct xe_reg_sr reg_sr;
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/** @reset: state for GT resets */
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struct {
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/**
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* @reset.worker: work so GT resets can done async allowing to reset
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* code to safely flush all code paths
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*/
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struct work_struct worker;
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} reset;
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/** @tlb_invalidation: TLB invalidation state */
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struct {
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/** @tlb_invalidation.seqno: TLB invalidation seqno, protected by CT lock */
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#define TLB_INVALIDATION_SEQNO_MAX 0x100000
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int seqno;
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/**
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* @tlb_invalidation.seqno_recv: last received TLB invalidation seqno,
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* protected by CT lock
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*/
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int seqno_recv;
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/**
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* @tlb_invalidation.pending_fences: list of pending fences waiting TLB
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* invaliations, protected by CT lock
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*/
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struct list_head pending_fences;
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/**
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* @tlb_invalidation.pending_lock: protects @tlb_invalidation.pending_fences
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* and updating @tlb_invalidation.seqno_recv.
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*/
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spinlock_t pending_lock;
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/**
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* @tlb_invalidation.fence_tdr: schedules a delayed call to
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* xe_gt_tlb_fence_timeout after the timeut interval is over.
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*/
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struct delayed_work fence_tdr;
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/** @tlb_invalidation.fence_context: context for TLB invalidation fences */
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u64 fence_context;
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/**
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* @tlb_invalidation.fence_seqno: seqno to TLB invalidation fences, protected by
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* tlb_invalidation.lock
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*/
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u32 fence_seqno;
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/** @tlb_invalidation.lock: protects TLB invalidation fences */
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spinlock_t lock;
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} tlb_invalidation;
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/**
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* @ccs_mode: Number of compute engines enabled.
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* Allows fixed mapping of available compute slices to compute engines.
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* By default only the first available compute engine is enabled and all
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* available compute slices are allocated to it.
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*/
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u32 ccs_mode;
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/** @usm: unified shared memory state */
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struct {
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/**
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* @usm.bb_pool: Pool from which batchbuffers, for USM operations
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* (e.g. migrations, fixing page tables), are allocated.
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* Dedicated pool needed so USM operations to not get blocked
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* behind any user operations which may have resulted in a
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* fault.
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*/
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struct xe_sa_manager *bb_pool;
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/**
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* @usm.reserved_bcs_instance: reserved BCS instance used for USM
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* operations (e.g. mmigrations, fixing page tables)
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*/
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u16 reserved_bcs_instance;
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/** @usm.pf_wq: page fault work queue, unbound, high priority */
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struct workqueue_struct *pf_wq;
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/** @usm.acc_wq: access counter work queue, unbound, high priority */
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struct workqueue_struct *acc_wq;
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/**
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* @usm.pf_queue: Page fault queue used to sync faults so faults can
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* be processed not under the GuC CT lock. The queue is sized so
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* it can sync all possible faults (1 per physical engine).
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* Multiple queues exists for page faults from different VMs are
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* be processed in parallel.
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*/
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struct pf_queue {
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/** @usm.pf_queue.gt: back pointer to GT */
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struct xe_gt *gt;
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#define PF_QUEUE_NUM_DW 128
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/** @usm.pf_queue.data: data in the page fault queue */
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u32 data[PF_QUEUE_NUM_DW];
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/**
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* @usm.pf_queue.tail: tail pointer in DWs for page fault queue,
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* moved by worker which processes faults (consumer).
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*/
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u16 tail;
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/**
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* @usm.pf_queue.head: head pointer in DWs for page fault queue,
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* moved by G2H handler (producer).
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*/
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u16 head;
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/** @usm.pf_queue.lock: protects page fault queue */
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spinlock_t lock;
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/** @usm.pf_queue.worker: to process page faults */
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struct work_struct worker;
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#define NUM_PF_QUEUE 4
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} pf_queue[NUM_PF_QUEUE];
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/**
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* @usm.acc_queue: Same as page fault queue, cannot process access
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* counters under CT lock.
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*/
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struct acc_queue {
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/** @usm.acc_queue.gt: back pointer to GT */
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struct xe_gt *gt;
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#define ACC_QUEUE_NUM_DW 128
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/** @usm.acc_queue.data: data in the page fault queue */
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u32 data[ACC_QUEUE_NUM_DW];
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/**
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* @usm.acc_queue.tail: tail pointer in DWs for access counter queue,
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* moved by worker which processes counters
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* (consumer).
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*/
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u16 tail;
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/**
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* @usm.acc_queue.head: head pointer in DWs for access counter queue,
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* moved by G2H handler (producer).
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*/
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u16 head;
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/** @usm.acc_queue.lock: protects page fault queue */
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spinlock_t lock;
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/** @usm.acc_queue.worker: to process access counters */
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struct work_struct worker;
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#define NUM_ACC_QUEUE 4
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} acc_queue[NUM_ACC_QUEUE];
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} usm;
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/** @ordered_wq: used to serialize GT resets and TDRs */
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struct workqueue_struct *ordered_wq;
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/** @uc: micro controllers on the GT */
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struct xe_uc uc;
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/** @gtidle: idle properties of GT */
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struct xe_gt_idle gtidle;
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/** @exec_queue_ops: submission backend exec queue operations */
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const struct xe_exec_queue_ops *exec_queue_ops;
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/**
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* @ring_ops: ring operations for this hw engine (1 per engine class)
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*/
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const struct xe_ring_ops *ring_ops[XE_ENGINE_CLASS_MAX];
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/** @fence_irq: fence IRQs (1 per engine class) */
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struct xe_hw_fence_irq fence_irq[XE_ENGINE_CLASS_MAX];
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/** @default_lrc: default LRC state */
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void *default_lrc[XE_ENGINE_CLASS_MAX];
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/** @hw_engines: hardware engines on the GT */
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struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES];
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/** @eclass: per hardware engine class interface on the GT */
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struct xe_hw_engine_class_intf eclass[XE_ENGINE_CLASS_MAX];
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/** @pcode: GT's PCODE */
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struct {
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/** @pcode.lock: protecting GT's PCODE mailbox data */
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struct mutex lock;
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} pcode;
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/** @sysfs: sysfs' kobj used by xe_gt_sysfs */
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struct kobject *sysfs;
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/** @freq: Main GT freq sysfs control */
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struct kobject *freq;
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/** @mocs: info */
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struct {
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/** @mocs.uc_index: UC index */
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u8 uc_index;
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/** @mocs.wb_index: WB index, only used on L3_CCS platforms */
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u8 wb_index;
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} mocs;
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/** @fuse_topo: GT topology reported by fuse registers */
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struct {
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/** @fuse_topo.g_dss_mask: dual-subslices usable by geometry */
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xe_dss_mask_t g_dss_mask;
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/** @fuse_topo.c_dss_mask: dual-subslices usable by compute */
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xe_dss_mask_t c_dss_mask;
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/** @fuse_topo.eu_mask_per_dss: EU mask per DSS*/
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xe_eu_mask_t eu_mask_per_dss;
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} fuse_topo;
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/** @steering: register steering for individual HW units */
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struct {
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/** @steering.ranges: register ranges used for this steering type */
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const struct xe_mmio_range *ranges;
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/** @steering.group_target: target to steer accesses to */
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u16 group_target;
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/** @steering.instance_target: instance to steer accesses to */
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u16 instance_target;
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} steering[NUM_STEERING_TYPES];
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/**
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* @mcr_lock: protects the MCR_SELECTOR register for the duration
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* of a steered operation
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*/
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spinlock_t mcr_lock;
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/** @wa_active: keep track of active workarounds */
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struct {
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/** @wa_active.gt: bitmap with active GT workarounds */
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unsigned long *gt;
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/** @wa_active.engine: bitmap with active engine workarounds */
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unsigned long *engine;
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/** @wa_active.lrc: bitmap with active LRC workarounds */
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unsigned long *lrc;
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/** @wa_active.oob: bitmap with active OOB workaroudns */
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unsigned long *oob;
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} wa_active;
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};
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#endif
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