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c43ca5091a
Add support for AMD Family 15h [and above] northbridge performance counters. MSRs 0xc0010240 ~ 0xc0010247 are shared across all cores that share a common northbridge. Add support for AMD Family 16h L2 performance counters. MSRs 0xc0010230 ~ 0xc0010237 are shared across all cores that share a common L2 cache. We do not enable counter overflow interrupts. Sampling mode and per-thread events are not supported. Signed-off-by: Jacob Shin <jacob.shin@amd.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: Stephane Eranian <eranian@google.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/20130419213428.GA8229@jshin-Toonie Signed-off-by: Ingo Molnar <mingo@kernel.org> |
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| .. | ||
| a.out.h | ||
| auxvec.h | ||
| bitsperlong.h | ||
| boot.h | ||
| bootparam.h | ||
| byteorder.h | ||
| debugreg.h | ||
| e820.h | ||
| errno.h | ||
| fcntl.h | ||
| hw_breakpoint.h | ||
| hyperv.h | ||
| ioctl.h | ||
| ioctls.h | ||
| ipcbuf.h | ||
| ist.h | ||
| Kbuild | ||
| kvm.h | ||
| kvm_para.h | ||
| ldt.h | ||
| mce.h | ||
| mman.h | ||
| msgbuf.h | ||
| msr-index.h | ||
| msr.h | ||
| mtrr.h | ||
| param.h | ||
| perf_regs.h | ||
| poll.h | ||
| posix_types.h | ||
| posix_types_32.h | ||
| posix_types_64.h | ||
| posix_types_x32.h | ||
| prctl.h | ||
| processor-flags.h | ||
| ptrace-abi.h | ||
| ptrace.h | ||
| resource.h | ||
| sembuf.h | ||
| setup.h | ||
| shmbuf.h | ||
| sigcontext.h | ||
| sigcontext32.h | ||
| siginfo.h | ||
| signal.h | ||
| socket.h | ||
| sockios.h | ||
| stat.h | ||
| statfs.h | ||
| svm.h | ||
| swab.h | ||
| termbits.h | ||
| termios.h | ||
| types.h | ||
| ucontext.h | ||
| unistd.h | ||
| vm86.h | ||
| vmx.h | ||
| vsyscall.h | ||