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SDHC Spec 3.0: Capabilities Register bits[15-08] are Base Clock Frequency 1.0/2.0: Capabilities Register bits[13-08] are Base Clock Frequency Signed-off-by: Zhangfei Gao <zgao6@marvell.com> Cc: David Vrabel <david.vrabel@csr.com> Cc: Matt Fleming <matt@console-pimps.org> Cc: Michal Miroslaw <mirqus@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Chris Ball <cjb@laptop.org> |
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