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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
211 lines
8.2 KiB
C
211 lines
8.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* arch/arm/mach-ep93xx/soc.h
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*
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* Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
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* Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
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*/
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#ifndef _EP93XX_SOC_H
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#define _EP93XX_SOC_H
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#include <mach/ep93xx-regs.h>
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/*
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* EP93xx Physical Memory Map:
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*
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* The ASDO pin is sampled at system reset to select a synchronous or
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* asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
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* the synchronous boot mode is selected. When ASDO is "0" (i.e
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* pulled-down) the asynchronous boot mode is selected.
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*
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* In synchronous boot mode nSDCE3 is decoded starting at physical address
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* 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
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* boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
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* decoded at 0xf0000000.
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*
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* There is known errata for the EP93xx dealing with External Memory
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* Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
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* Guidelines" for more information. This document can be found at:
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*
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* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
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*/
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#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
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#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
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#define EP93XX_CS1_PHYS_BASE 0x10000000
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#define EP93XX_CS2_PHYS_BASE 0x20000000
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#define EP93XX_CS3_PHYS_BASE 0x30000000
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#define EP93XX_PCMCIA_PHYS_BASE 0x40000000
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#define EP93XX_CS6_PHYS_BASE 0x60000000
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#define EP93XX_CS7_PHYS_BASE 0x70000000
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#define EP93XX_SDCE0_PHYS_BASE 0xc0000000
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#define EP93XX_SDCE1_PHYS_BASE 0xd0000000
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#define EP93XX_SDCE2_PHYS_BASE 0xe0000000
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#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
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#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
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/* AHB peripherals */
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#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
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#define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000)
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#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
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#define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000)
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#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
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#define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000)
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#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
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#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
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#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
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#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
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#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
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#define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000)
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#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
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#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
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#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
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/* APB peripherals */
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#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
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#define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
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#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
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#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
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#define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
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#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
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#define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000)
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#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
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#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
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#define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000)
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#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
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#define EP93XX_ADC_PHYS_BASE EP93XX_APB_PHYS(0x00100000)
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#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
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#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
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#define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000)
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#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
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#define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000)
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#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
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#define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000)
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#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
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/* System controller */
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#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
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#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
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#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
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#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
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#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
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#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
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#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
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#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
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#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
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#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
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#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
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#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
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#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
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#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
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#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
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#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
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#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
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#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
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#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
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#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
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#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
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#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
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#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
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#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
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#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
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#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
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#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
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#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
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#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
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#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
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#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
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#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
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#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
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#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
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#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
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#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
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#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
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#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
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#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
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#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
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#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
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#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
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#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
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#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
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#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
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#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
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#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
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#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
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#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
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#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
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#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
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#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
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#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
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#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
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#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
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#define EP93XX_I2SCLKDIV_SDIV (1 << 16)
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#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
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#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
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#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
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#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
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#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
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#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
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#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
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#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
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#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
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#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
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#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
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#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
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#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
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#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
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#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
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#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
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#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
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#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
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#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
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#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
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#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
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/* EP93xx System Controller software locked register write */
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void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
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void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
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static inline void ep93xx_devcfg_set_bits(unsigned int bits)
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{
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ep93xx_devcfg_set_clear(bits, 0x00);
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}
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static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
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{
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ep93xx_devcfg_set_clear(0x00, bits);
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}
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#endif /* _EP93XX_SOC_H */
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