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2907cf3f2e
commit950b879b7fupstream. In commit588a513d34("arm64: Fix race condition on PG_dcache_clean in __sync_icache_dcache()"), we found RISC-V has the same issue as the previous arm64. The previous implementation didn't guarantee the correct sequence of operations, which means flush_icache_all() hasn't been called when the PG_dcache_clean was set. That would cause a risk of page synchronization. Fixes:08f051eda3("RISC-V: Flush I$ when making a dirty page executable") Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230127035306.1819561-1-guoren@kernel.org Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
93 lines
2.5 KiB
C
93 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 SiFive
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*/
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#include <asm/cacheflush.h>
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#ifdef CONFIG_SMP
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#include <asm/sbi.h>
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static void ipi_remote_fence_i(void *info)
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{
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return local_flush_icache_all();
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}
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void flush_icache_all(void)
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{
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local_flush_icache_all();
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if (IS_ENABLED(CONFIG_RISCV_SBI))
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sbi_remote_fence_i(NULL);
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else
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on_each_cpu(ipi_remote_fence_i, NULL, 1);
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}
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EXPORT_SYMBOL(flush_icache_all);
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/*
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* Performs an icache flush for the given MM context. RISC-V has no direct
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* mechanism for instruction cache shoot downs, so instead we send an IPI that
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* informs the remote harts they need to flush their local instruction caches.
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* To avoid pathologically slow behavior in a common case (a bunch of
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* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
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* IPIs for harts that are not currently executing a MM context and instead
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* schedule a deferred local instruction cache flush to be performed before
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* execution resumes on each hart.
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*/
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void flush_icache_mm(struct mm_struct *mm, bool local)
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{
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unsigned int cpu;
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cpumask_t others, *mask;
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preempt_disable();
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/* Mark every hart's icache as needing a flush for this MM. */
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mask = &mm->context.icache_stale_mask;
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cpumask_setall(mask);
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/* Flush this hart's I$ now, and mark it as flushed. */
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mask);
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local_flush_icache_all();
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/*
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* Flush the I$ of other harts concurrently executing, and mark them as
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* flushed.
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*/
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cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
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local |= cpumask_empty(&others);
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if (mm == current->active_mm && local) {
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/*
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* It's assumed that at least one strongly ordered operation is
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* performed on this hart between setting a hart's cpumask bit
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* and scheduling this MM context on that hart. Sending an SBI
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* remote message will do this, but in the case where no
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* messages are sent we still need to order this hart's writes
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* with flush_icache_deferred().
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*/
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smp_mb();
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} else if (IS_ENABLED(CONFIG_RISCV_SBI)) {
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cpumask_t hartid_mask;
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riscv_cpuid_to_hartid_mask(&others, &hartid_mask);
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sbi_remote_fence_i(cpumask_bits(&hartid_mask));
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} else {
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on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
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}
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preempt_enable();
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}
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_MMU
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void flush_icache_pte(pte_t pte)
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{
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struct page *page = pte_page(pte);
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if (!test_bit(PG_dcache_clean, &page->flags)) {
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flush_icache_all();
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set_bit(PG_dcache_clean, &page->flags);
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}
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}
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#endif /* CONFIG_MMU */
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