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![Xiubo Li](/assets/img/avatar_default.png)
Since msleep() will sleep longer than intended time for values less than 20ms, this patch allows the use of usleep_range for just 1ms. usleep_range is a finer precision implementation of msleep and is designed to be a drop-in replacement for udelay where a precise sleep/busy-wait is unnecessary. More details see Documentation/timers/timers-howto.txt. Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com> Signed-off-by: Mark Brown <broonie@kernel.org>
351 lines
9 KiB
C
351 lines
9 KiB
C
/*
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* linux/sound/mpc5200-ac97.c -- AC97 support for the Freescale MPC52xx chip.
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*
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* Copyright (C) 2009 Jon Smirl, Digispeaker
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* Author: Jon Smirl <jonsmirl@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/delay.h>
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#include <linux/time.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <asm/time.h>
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#include <asm/delay.h>
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#include <asm/mpc52xx.h>
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#include <asm/mpc52xx_psc.h>
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#include "mpc5200_dma.h"
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#include "mpc5200_psc_ac97.h"
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#define DRV_NAME "mpc5200-psc-ac97"
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/* ALSA only supports a single AC97 device so static is recommend here */
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static struct psc_dma *psc_dma;
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static unsigned short psc_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
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{
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int status;
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unsigned int val;
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mutex_lock(&psc_dma->mutex);
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/* Wait for command send status zero = ready */
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status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
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MPC52xx_PSC_SR_CMDSEND), 100, 0);
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if (status == 0) {
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pr_err("timeout on ac97 bus (rdy)\n");
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mutex_unlock(&psc_dma->mutex);
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return -ENODEV;
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}
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/* Force clear the data valid bit */
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in_be32(&psc_dma->psc_regs->ac97_data);
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/* Send the read */
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out_be32(&psc_dma->psc_regs->ac97_cmd, (1<<31) | ((reg & 0x7f) << 24));
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/* Wait for the answer */
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status = spin_event_timeout((in_be16(&psc_dma->psc_regs->sr_csr.status) &
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MPC52xx_PSC_SR_DATA_VAL), 100, 0);
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if (status == 0) {
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pr_err("timeout on ac97 read (val) %x\n",
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in_be16(&psc_dma->psc_regs->sr_csr.status));
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mutex_unlock(&psc_dma->mutex);
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return -ENODEV;
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}
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/* Get the data */
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val = in_be32(&psc_dma->psc_regs->ac97_data);
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if (((val >> 24) & 0x7f) != reg) {
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pr_err("reg echo error on ac97 read\n");
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mutex_unlock(&psc_dma->mutex);
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return -ENODEV;
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}
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val = (val >> 8) & 0xffff;
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mutex_unlock(&psc_dma->mutex);
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return (unsigned short) val;
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}
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static void psc_ac97_write(struct snd_ac97 *ac97,
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unsigned short reg, unsigned short val)
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{
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int status;
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mutex_lock(&psc_dma->mutex);
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/* Wait for command status zero = ready */
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status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
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MPC52xx_PSC_SR_CMDSEND), 100, 0);
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if (status == 0) {
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pr_err("timeout on ac97 bus (write)\n");
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goto out;
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}
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/* Write data */
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out_be32(&psc_dma->psc_regs->ac97_cmd,
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((reg & 0x7f) << 24) | (val << 8));
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out:
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mutex_unlock(&psc_dma->mutex);
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}
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static void psc_ac97_warm_reset(struct snd_ac97 *ac97)
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{
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struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
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mutex_lock(&psc_dma->mutex);
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out_be32(®s->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_AWR);
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udelay(3);
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out_be32(®s->sicr, psc_dma->sicr);
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mutex_unlock(&psc_dma->mutex);
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}
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static void psc_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
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mutex_lock(&psc_dma->mutex);
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dev_dbg(psc_dma->dev, "cold reset\n");
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mpc5200_psc_ac97_gpio_reset(psc_dma->id);
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/* Notify the PSC that a reset has occurred */
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out_be32(®s->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_ACRB);
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/* Re-enable RX and TX */
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out_8(®s->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
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mutex_unlock(&psc_dma->mutex);
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usleep_range(1000, 2000);
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psc_ac97_warm_reset(ac97);
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}
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static struct snd_ac97_bus_ops psc_ac97_ops = {
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.read = psc_ac97_read,
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.write = psc_ac97_write,
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.reset = psc_ac97_cold_reset,
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.warm_reset = psc_ac97_warm_reset,
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};
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static int psc_ac97_hw_analog_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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{
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struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
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struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
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dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i"
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" periods=%i buffer_size=%i buffer_bytes=%i channels=%i"
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" rate=%i format=%i\n",
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__func__, substream, params_period_size(params),
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params_period_bytes(params), params_periods(params),
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params_buffer_size(params), params_buffer_bytes(params),
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params_channels(params), params_rate(params),
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params_format(params));
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/* Determine the set of enable bits to turn on */
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s->ac97_slot_bits = (params_channels(params) == 1) ? 0x100 : 0x300;
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if (substream->pstr->stream != SNDRV_PCM_STREAM_CAPTURE)
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s->ac97_slot_bits <<= 16;
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return 0;
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}
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static int psc_ac97_hw_digital_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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{
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struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
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dev_dbg(psc_dma->dev, "%s(substream=%p)\n", __func__, substream);
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if (params_channels(params) == 1)
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out_be32(&psc_dma->psc_regs->ac97_slots, 0x01000000);
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else
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out_be32(&psc_dma->psc_regs->ac97_slots, 0x03000000);
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return 0;
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}
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static int psc_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(dai);
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struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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dev_dbg(psc_dma->dev, "AC97 START: stream=%i\n",
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substream->pstr->stream);
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/* Set the slot enable bits */
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psc_dma->slots |= s->ac97_slot_bits;
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out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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dev_dbg(psc_dma->dev, "AC97 STOP: stream=%i\n",
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substream->pstr->stream);
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/* Clear the slot enable bits */
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psc_dma->slots &= ~(s->ac97_slot_bits);
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out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
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break;
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}
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return 0;
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}
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static int psc_ac97_probe(struct snd_soc_dai *cpu_dai)
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{
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struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
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struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
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/* Go */
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out_8(®s->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
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return 0;
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}
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/* ---------------------------------------------------------------------
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* ALSA SoC Bindings
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*
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* - Digital Audio Interface (DAI) template
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* - create/destroy dai hooks
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*/
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/**
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* psc_ac97_dai_template: template CPU Digital Audio Interface
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*/
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static const struct snd_soc_dai_ops psc_ac97_analog_ops = {
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.hw_params = psc_ac97_hw_analog_params,
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.trigger = psc_ac97_trigger,
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};
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static const struct snd_soc_dai_ops psc_ac97_digital_ops = {
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.hw_params = psc_ac97_hw_digital_params,
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};
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static struct snd_soc_dai_driver psc_ac97_dai[] = {
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{
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.name = "mpc5200-psc-ac97.0",
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.bus_control = true,
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.probe = psc_ac97_probe,
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.playback = {
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.stream_name = "AC97 Playback",
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.channels_min = 1,
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.channels_max = 6,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S32_BE,
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},
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.capture = {
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.stream_name = "AC97 Capture",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S32_BE,
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},
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.ops = &psc_ac97_analog_ops,
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},
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{
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.name = "mpc5200-psc-ac97.1",
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.bus_control = true,
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.playback = {
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.stream_name = "AC97 SPDIF",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_32000 | \
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SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
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.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE,
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},
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.ops = &psc_ac97_digital_ops,
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} };
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static const struct snd_soc_component_driver psc_ac97_component = {
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.name = DRV_NAME,
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};
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/* ---------------------------------------------------------------------
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* OF platform bus binding code:
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* - Probe/remove operations
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* - OF device match table
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*/
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static int psc_ac97_of_probe(struct platform_device *op)
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{
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int rc;
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struct mpc52xx_psc __iomem *regs;
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rc = mpc5200_audio_dma_create(op);
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if (rc != 0)
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return rc;
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rc = snd_soc_set_ac97_ops(&psc_ac97_ops);
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if (rc != 0) {
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dev_err(&op->dev, "Failed to set AC'97 ops: %d\n", rc);
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return rc;
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}
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rc = snd_soc_register_component(&op->dev, &psc_ac97_component,
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psc_ac97_dai, ARRAY_SIZE(psc_ac97_dai));
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if (rc != 0) {
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dev_err(&op->dev, "Failed to register DAI\n");
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return rc;
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}
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psc_dma = dev_get_drvdata(&op->dev);
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regs = psc_dma->psc_regs;
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psc_dma->imr = 0;
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out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
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/* Configure the serial interface mode to AC97 */
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psc_dma->sicr = MPC52xx_PSC_SICR_SIM_AC97 | MPC52xx_PSC_SICR_ENAC97;
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out_be32(®s->sicr, psc_dma->sicr);
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/* No slots active */
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out_be32(®s->ac97_slots, 0x00000000);
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return 0;
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}
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static int psc_ac97_of_remove(struct platform_device *op)
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{
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mpc5200_audio_dma_destroy(op);
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snd_soc_unregister_component(&op->dev);
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snd_soc_set_ac97_ops(NULL);
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return 0;
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}
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/* Match table for of_platform binding */
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static const struct of_device_id psc_ac97_match[] = {
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{ .compatible = "fsl,mpc5200-psc-ac97", },
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{ .compatible = "fsl,mpc5200b-psc-ac97", },
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{}
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};
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MODULE_DEVICE_TABLE(of, psc_ac97_match);
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static struct platform_driver psc_ac97_driver = {
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.probe = psc_ac97_of_probe,
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.remove = psc_ac97_of_remove,
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.driver = {
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.name = "mpc5200-psc-ac97",
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.of_match_table = psc_ac97_match,
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},
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};
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module_platform_driver(psc_ac97_driver);
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MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
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MODULE_DESCRIPTION("mpc5200 AC97 module");
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MODULE_LICENSE("GPL");
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