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![Stephen Warren](/assets/img/avatar_default.png)
Tegra124 introduces some small changes to the layout of some registers. Modify the affected drivers to program those registers appropriately based on which SoC they're running on. Tegra124 also introduced some new modules on the AHUB configlink register bus. These will require new entries in configlink_clocks[] in the AHUB driver. However, supporting that change likely relies on switching Tegra to the common reset framework, so I'll defer that change for now. Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com> Based-on-work-by: Songhee Baek <sbaek@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
240 lines
5.8 KiB
C
240 lines
5.8 KiB
C
/*
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* tegra_asoc_utils.c - Harmony machine ASoC driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2010,2012 - NVIDIA, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include "tegra_asoc_utils.h"
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int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
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int mclk)
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{
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int new_baseclock;
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bool clk_change;
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int err;
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switch (srate) {
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case 11025:
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case 22050:
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case 44100:
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case 88200:
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if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
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new_baseclock = 56448000;
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else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
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new_baseclock = 564480000;
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else
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new_baseclock = 282240000;
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break;
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case 8000:
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case 16000:
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case 32000:
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case 48000:
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case 64000:
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case 96000:
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if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
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new_baseclock = 73728000;
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else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
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new_baseclock = 552960000;
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else
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new_baseclock = 368640000;
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break;
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default:
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return -EINVAL;
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}
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clk_change = ((new_baseclock != data->set_baseclock) ||
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(mclk != data->set_mclk));
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if (!clk_change)
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return 0;
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data->set_baseclock = 0;
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data->set_mclk = 0;
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clk_disable_unprepare(data->clk_cdev1);
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clk_disable_unprepare(data->clk_pll_a_out0);
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clk_disable_unprepare(data->clk_pll_a);
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err = clk_set_rate(data->clk_pll_a, new_baseclock);
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if (err) {
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dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
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return err;
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}
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err = clk_set_rate(data->clk_pll_a_out0, mclk);
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if (err) {
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dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
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return err;
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}
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/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
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err = clk_prepare_enable(data->clk_pll_a);
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if (err) {
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dev_err(data->dev, "Can't enable pll_a: %d\n", err);
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return err;
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}
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err = clk_prepare_enable(data->clk_pll_a_out0);
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if (err) {
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dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
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return err;
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}
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err = clk_prepare_enable(data->clk_cdev1);
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if (err) {
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dev_err(data->dev, "Can't enable cdev1: %d\n", err);
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return err;
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}
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data->set_baseclock = new_baseclock;
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data->set_mclk = mclk;
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_rate);
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int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data)
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{
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const int pll_rate = 73728000;
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const int ac97_rate = 24576000;
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int err;
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clk_disable_unprepare(data->clk_cdev1);
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clk_disable_unprepare(data->clk_pll_a_out0);
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clk_disable_unprepare(data->clk_pll_a);
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/*
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* AC97 rate is fixed at 24.576MHz and is used for both the host
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* controller and the external codec
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*/
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err = clk_set_rate(data->clk_pll_a, pll_rate);
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if (err) {
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dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
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return err;
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}
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err = clk_set_rate(data->clk_pll_a_out0, ac97_rate);
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if (err) {
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dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
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return err;
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}
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/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
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err = clk_prepare_enable(data->clk_pll_a);
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if (err) {
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dev_err(data->dev, "Can't enable pll_a: %d\n", err);
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return err;
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}
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err = clk_prepare_enable(data->clk_pll_a_out0);
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if (err) {
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dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
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return err;
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}
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err = clk_prepare_enable(data->clk_cdev1);
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if (err) {
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dev_err(data->dev, "Can't enable cdev1: %d\n", err);
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return err;
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}
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data->set_baseclock = pll_rate;
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data->set_mclk = ac97_rate;
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate);
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int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
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struct device *dev)
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{
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int ret;
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data->dev = dev;
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if (of_machine_is_compatible("nvidia,tegra20"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20;
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else if (of_machine_is_compatible("nvidia,tegra30"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30;
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else if (of_machine_is_compatible("nvidia,tegra114"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA114;
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else if (of_machine_is_compatible("nvidia,tegra124"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA124;
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else {
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dev_err(data->dev, "SoC unknown to Tegra ASoC utils\n");
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return -EINVAL;
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}
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data->clk_pll_a = clk_get(dev, "pll_a");
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if (IS_ERR(data->clk_pll_a)) {
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dev_err(data->dev, "Can't retrieve clk pll_a\n");
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ret = PTR_ERR(data->clk_pll_a);
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goto err;
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}
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data->clk_pll_a_out0 = clk_get(dev, "pll_a_out0");
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if (IS_ERR(data->clk_pll_a_out0)) {
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dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
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ret = PTR_ERR(data->clk_pll_a_out0);
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goto err_put_pll_a;
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}
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data->clk_cdev1 = clk_get(dev, "mclk");
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if (IS_ERR(data->clk_cdev1)) {
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dev_err(data->dev, "Can't retrieve clk cdev1\n");
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ret = PTR_ERR(data->clk_cdev1);
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goto err_put_pll_a_out0;
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}
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ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
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if (ret)
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goto err_put_cdev1;
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return 0;
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err_put_cdev1:
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clk_put(data->clk_cdev1);
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err_put_pll_a_out0:
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clk_put(data->clk_pll_a_out0);
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err_put_pll_a:
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clk_put(data->clk_pll_a);
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err:
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return ret;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
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void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
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{
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clk_put(data->clk_cdev1);
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clk_put(data->clk_pll_a_out0);
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clk_put(data->clk_pll_a);
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
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MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
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MODULE_DESCRIPTION("Tegra ASoC utility code");
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MODULE_LICENSE("GPL");
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