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e5745f3411
Add support for HW QAT Power Management (PM) feature. This feature is enabled at init time (1) by sending an admin message to the firmware, targeting the admin AE, that sets the idle time before the device changes state and (2) by unmasking the PM source of interrupt in ERRMSK2. The interrupt handler is extended to handle a PM interrupt which is triggered by HW when a PM transition occurs. In this case, the driver responds acknowledging the transaction using the HOST_MSG mailbox. Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Co-developed-by: Marcinx Malinowski <marcinx.malinowski@intel.com> Signed-off-by: Marcinx Malinowski <marcinx.malinowski@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Marco Chiappero <marco.chiappero@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
137 lines
3.5 KiB
C
137 lines
3.5 KiB
C
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
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/* Copyright(c) 2022 Intel Corporation */
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#include <linux/bitfield.h>
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#include <linux/iopoll.h>
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#include "adf_accel_devices.h"
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#include "adf_common_drv.h"
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#include "adf_gen4_pm.h"
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#include "adf_cfg_strings.h"
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#include "icp_qat_fw_init_admin.h"
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#include "adf_gen4_hw_data.h"
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#include "adf_cfg.h"
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enum qat_pm_host_msg {
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PM_NO_CHANGE = 0,
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PM_SET_MIN,
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};
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struct adf_gen4_pm_data {
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struct work_struct pm_irq_work;
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struct adf_accel_dev *accel_dev;
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u32 pm_int_sts;
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};
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static int send_host_msg(struct adf_accel_dev *accel_dev)
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{
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void __iomem *pmisc = adf_get_pmisc_base(accel_dev);
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u32 msg;
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msg = ADF_CSR_RD(pmisc, ADF_GEN4_PM_HOST_MSG);
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if (msg & ADF_GEN4_PM_MSG_PENDING)
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return -EBUSY;
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/* Send HOST_MSG */
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msg = FIELD_PREP(ADF_GEN4_PM_MSG_PAYLOAD_BIT_MASK, PM_SET_MIN);
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msg |= ADF_GEN4_PM_MSG_PENDING;
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ADF_CSR_WR(pmisc, ADF_GEN4_PM_HOST_MSG, msg);
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/* Poll status register to make sure the HOST_MSG has been processed */
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return read_poll_timeout(ADF_CSR_RD, msg,
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!(msg & ADF_GEN4_PM_MSG_PENDING),
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ADF_GEN4_PM_MSG_POLL_DELAY_US,
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ADF_GEN4_PM_POLL_TIMEOUT_US, true, pmisc,
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ADF_GEN4_PM_HOST_MSG);
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}
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static void pm_bh_handler(struct work_struct *work)
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{
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struct adf_gen4_pm_data *pm_data =
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container_of(work, struct adf_gen4_pm_data, pm_irq_work);
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struct adf_accel_dev *accel_dev = pm_data->accel_dev;
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void __iomem *pmisc = adf_get_pmisc_base(accel_dev);
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u32 pm_int_sts = pm_data->pm_int_sts;
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u32 val;
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/* PM Idle interrupt */
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if (pm_int_sts & ADF_GEN4_PM_IDLE_STS) {
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/* Issue host message to FW */
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if (send_host_msg(accel_dev))
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dev_warn_ratelimited(&GET_DEV(accel_dev),
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"Failed to send host msg to FW\n");
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}
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/* Clear interrupt status */
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ADF_CSR_WR(pmisc, ADF_GEN4_PM_INTERRUPT, pm_int_sts);
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/* Reenable PM interrupt */
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val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2);
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val &= ~ADF_GEN4_PM_SOU;
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ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val);
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kfree(pm_data);
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}
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bool adf_gen4_handle_pm_interrupt(struct adf_accel_dev *accel_dev)
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{
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void __iomem *pmisc = adf_get_pmisc_base(accel_dev);
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struct adf_gen4_pm_data *pm_data = NULL;
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u32 errsou2;
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u32 errmsk2;
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u32 val;
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/* Only handle the interrupt triggered by PM */
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errmsk2 = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2);
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if (errmsk2 & ADF_GEN4_PM_SOU)
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return false;
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errsou2 = ADF_CSR_RD(pmisc, ADF_GEN4_ERRSOU2);
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if (!(errsou2 & ADF_GEN4_PM_SOU))
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return false;
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/* Disable interrupt */
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val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2);
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val |= ADF_GEN4_PM_SOU;
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ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val);
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val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_INTERRUPT);
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pm_data = kzalloc(sizeof(*pm_data), GFP_ATOMIC);
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if (!pm_data)
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return false;
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pm_data->pm_int_sts = val;
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pm_data->accel_dev = accel_dev;
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INIT_WORK(&pm_data->pm_irq_work, pm_bh_handler);
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adf_misc_wq_queue_work(&pm_data->pm_irq_work);
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return true;
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}
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EXPORT_SYMBOL_GPL(adf_gen4_handle_pm_interrupt);
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int adf_gen4_enable_pm(struct adf_accel_dev *accel_dev)
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{
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void __iomem *pmisc = adf_get_pmisc_base(accel_dev);
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int ret;
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u32 val;
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ret = adf_init_admin_pm(accel_dev, ADF_GEN4_PM_DEFAULT_IDLE_FILTER);
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if (ret)
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return ret;
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/* Enable default PM interrupts: IDLE, THROTTLE */
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val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_INTERRUPT);
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val |= ADF_GEN4_PM_INT_EN_DEFAULT;
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/* Clear interrupt status */
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val |= ADF_GEN4_PM_INT_STS_MASK;
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ADF_CSR_WR(pmisc, ADF_GEN4_PM_INTERRUPT, val);
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/* Unmask PM Interrupt */
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val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2);
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val &= ~ADF_GEN4_PM_SOU;
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ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val);
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return 0;
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}
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EXPORT_SYMBOL_GPL(adf_gen4_enable_pm);
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