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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation 51 franklin street fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 67 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141333.953658117@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
132 lines
3.1 KiB
ArmAsm
132 lines
3.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* Copyright SUSE Linux Products GmbH 2009
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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/******************************************************************************
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* *
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* Entry code *
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* *
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*****************************************************************************/
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.macro LOAD_GUEST_SEGMENTS
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/* Required state:
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*
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* MSR = ~IR|DR
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* R1 = host R1
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* R2 = host R2
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* R3 = shadow vcpu
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* all other volatile GPRS = free except R4, R6
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* SVCPU[CR] = guest CR
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* SVCPU[XER] = guest XER
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* SVCPU[CTR] = guest CTR
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* SVCPU[LR] = guest LR
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*/
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#define XCHG_SR(n) lwz r9, (SVCPU_SR+(n*4))(r3); \
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mtsr n, r9
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XCHG_SR(0)
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XCHG_SR(1)
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XCHG_SR(2)
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XCHG_SR(3)
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XCHG_SR(4)
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XCHG_SR(5)
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XCHG_SR(6)
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XCHG_SR(7)
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XCHG_SR(8)
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XCHG_SR(9)
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XCHG_SR(10)
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XCHG_SR(11)
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XCHG_SR(12)
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XCHG_SR(13)
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XCHG_SR(14)
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XCHG_SR(15)
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/* Clear BATs. */
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#define KVM_KILL_BAT(n, reg) \
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mtspr SPRN_IBAT##n##U,reg; \
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mtspr SPRN_IBAT##n##L,reg; \
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mtspr SPRN_DBAT##n##U,reg; \
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mtspr SPRN_DBAT##n##L,reg; \
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li r9, 0
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KVM_KILL_BAT(0, r9)
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KVM_KILL_BAT(1, r9)
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KVM_KILL_BAT(2, r9)
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KVM_KILL_BAT(3, r9)
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.endm
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/******************************************************************************
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* *
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* Exit code *
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* *
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*****************************************************************************/
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.macro LOAD_HOST_SEGMENTS
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/* Register usage at this point:
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*
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* R1 = host R1
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* R2 = host R2
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* R12 = exit handler id
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* R13 = shadow vcpu - SHADOW_VCPU_OFF
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* SVCPU.* = guest *
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* SVCPU[CR] = guest CR
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* SVCPU[XER] = guest XER
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* SVCPU[CTR] = guest CTR
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* SVCPU[LR] = guest LR
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*
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*/
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/* Restore BATs */
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/* We only overwrite the upper part, so we only restoree
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the upper part. */
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#define KVM_LOAD_BAT(n, reg, RA, RB) \
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lwz RA,(n*16)+0(reg); \
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lwz RB,(n*16)+4(reg); \
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mtspr SPRN_IBAT##n##U,RA; \
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mtspr SPRN_IBAT##n##L,RB; \
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lwz RA,(n*16)+8(reg); \
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lwz RB,(n*16)+12(reg); \
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mtspr SPRN_DBAT##n##U,RA; \
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mtspr SPRN_DBAT##n##L,RB; \
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lis r9, BATS@ha
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addi r9, r9, BATS@l
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tophys(r9, r9)
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KVM_LOAD_BAT(0, r9, r10, r11)
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KVM_LOAD_BAT(1, r9, r10, r11)
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KVM_LOAD_BAT(2, r9, r10, r11)
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KVM_LOAD_BAT(3, r9, r10, r11)
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/* Restore Segment Registers */
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/* 0xc - 0xf */
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li r0, 4
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mtctr r0
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LOAD_REG_IMMEDIATE(r3, 0x20000000 | (0x111 * 0xc))
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lis r4, 0xc000
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3: mtsrin r3, r4
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addi r3, r3, 0x111 /* increment VSID */
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addis r4, r4, 0x1000 /* address of next segment */
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bdnz 3b
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/* 0x0 - 0xb */
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/* 'current->mm' needs to be in r4 */
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tophys(r4, r2)
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lwz r4, MM(r4)
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tophys(r4, r4)
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/* This only clobbers r0, r3, r4 and r5 */
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bl switch_mmu_context
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.endm
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