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c6c003af0b
With the latest device tree reorganization which introduced the 'internal-reg' node, now the only region translated is the internal register's. This makes the description of the hardware incomplete, for it lacks the Device Bus childs address space. In order to fix this, it's required to add a 'ranges' entry with a suitable address space to map Device Bus childs, on a per-board basis. This patch fixes the ranges property on the Armada XP GP board. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
170 lines
3.6 KiB
Text
170 lines
3.6 KiB
Text
/*
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* Device Tree file for Marvell Armada XP development board
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* (DB-MV784MP-GP)
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*
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* Copyright (C) 2013 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/include/ "armada-xp-mv78460.dtsi"
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/ {
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model = "Marvell Armada XP Development Board DB-MV784MP-GP";
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compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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memory {
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device_type = "memory";
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/*
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* 8 GB of plug-in RAM modules by default.The amount
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* of memory available can be changed by the
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* bootloader according the size of the module
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* actually plugged. Only 7GB are usable because
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* addresses from 0xC0000000 to 0xffffffff are used by
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* the internal registers of the SoC.
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*/
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reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
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<0x00000001 0x00000000 0x00000001 0x00000000>;
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};
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soc {
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ranges = <0 0 0xd0000000 0x100000
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0xf0000000 0 0xf0000000 0x1000000>;
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internal-regs {
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serial@12000 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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serial@12100 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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serial@12200 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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serial@12300 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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sata@a0000 {
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nr-ports = <2>;
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status = "okay";
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};
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mdio {
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phy0: ethernet-phy@0 {
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reg = <16>;
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};
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phy1: ethernet-phy@1 {
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reg = <17>;
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};
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phy2: ethernet-phy@2 {
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reg = <18>;
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};
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phy3: ethernet-phy@3 {
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reg = <19>;
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};
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ethernet@74000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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ethernet@30000 {
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status = "okay";
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phy = <&phy2>;
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phy-mode = "rgmii-id";
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};
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ethernet@34000 {
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status = "okay";
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phy = <&phy3>;
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phy-mode = "rgmii-id";
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};
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spi0: spi@10600 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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devbus-bootcs@10400 {
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status = "okay";
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ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
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/* Device Bus parameters are required */
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/* Read parameters */
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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/* NOR 16 MiB */
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nor@0 {
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compatible = "cfi-flash";
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reg = <0 0x1000000>;
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bank-width = <2>;
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* The 3 slots are physically present as
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@10,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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};
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