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dc825b1790
This implements support for hardware-managed IRQ balancing as implemented by SH-X3 cores (presently only hooked up for SH7786, but can probably be carried over to other SH-X3 cores, too). CPUs need to specify their distribution register along with the mask definitions, as these follow the same format. Peripheral IRQs that don't opt out of balancing will be automatically distributed at the whim of the hardware block, while each CPU needs to verify whether it is handling the IRQ or not, especially before clearing the mask. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
24 lines
806 B
Text
24 lines
806 B
Text
config INTC_USERIMASK
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bool "Userspace interrupt masking support"
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depends on ARCH_SHMOBILE || (SUPERH && CPU_SH4A)
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help
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This enables support for hardware-assisted userspace hardirq
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masking.
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SH-4A and newer interrupt blocks all support a special shadowed
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page with all non-masking registers obscured when mapped in to
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userspace. This is primarily for use by userspace device
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drivers that are using special priority levels.
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If in doubt, say N.
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config INTC_BALANCING
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bool "Hardware IRQ balancing support"
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depends on SMP && SUPERH && CPU_SUBTYPE_SH7786
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help
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This enables support for IRQ auto-distribution mode on SH-X3
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SMP parts. All of the balancing and CPU wakeup decisions are
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taken care of automatically by hardware for distributed
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vectors.
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If in doubt, say N.
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