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![]() On many older systems using SW sequencer the PREOP_OPTYPE register contains two preopcodes as following: PREOP_OPTYPE=0xf2785006 The last two bytes are the opcodes decoded to: 0x50 - Write enable for volatile status register 0x06 - Write enable The former is used to modify volatile bits in the status register. For non-volatile bits the latter is needed. Preopcodes are used in SW sequencer to send one command "atomically" without anything else interfering the transfer. The sequence that gets executed is: - Send preopcode (write enable) from PREOP_OPTYPE register - Send the actual SPI command - Poll busy bit in the status register (0x05, RDSR) Commit |
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.. | ||
aspeed-smc.c | ||
atmel-quadspi.c | ||
cadence-quadspi.c | ||
fsl-quadspi.c | ||
hisi-sfc.c | ||
intel-spi-pci.c | ||
intel-spi-platform.c | ||
intel-spi.c | ||
intel-spi.h | ||
Kconfig | ||
Makefile | ||
mtk-quadspi.c | ||
nxp-spifi.c | ||
spi-nor.c | ||
stm32-quadspi.c |