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![Arnd Bergmann](/assets/img/avatar_default.png)
Almost all machines use GENERIC_CLOCKEVENTS, so it feels wrong to require each one to select that symbol manually. Instead, enable it whenever CONFIG_LEGACY_TIMER_TICK is disabled as a simplification. It should be possible to select both GENERIC_CLOCKEVENTS and LEGACY_TIMER_TICK from an architecture now and decide at runtime between the two. For the clockevents arch-support.txt file, this means that additional architectures are marked as TODO when they have at least one machine that still uses LEGACY_TIMER_TICK, rather than being marked 'ok' when at least one machine has been converted. This means that both m68k and arm (for riscpc) revert to TODO. At this point, we could just always enable CONFIG_GENERIC_CLOCKEVENTS rather than leaving it off when not needed. I built an m68k defconfig kernel (using gcc-10.1.0) and found that this would add around 5.5KB in kernel image size: text data bss dec hex filename 3861936 1092236 196656 5150828 4e986c obj-m68k/vmlinux-no-clockevent 3866201 1093832 196184 5156217 4ead79 obj-m68k/vmlinux-clockevent On Arm (MACH_RPC), that difference appears to be twice as large, around 11KB on top of an 6MB vmlinux. Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
196 lines
4.6 KiB
Text
196 lines
4.6 KiB
Text
# SPDX-License-Identifier: GPL-2.0
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#
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# For a description of the syntax of this configuration file,
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# see Documentation/kbuild/kconfig-language.rst.
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#
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config OPENRISC
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def_bool y
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select ARCH_32BIT_OFF_T
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select ARCH_HAS_DMA_SET_UNCACHED
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select ARCH_HAS_DMA_CLEAR_UNCACHED
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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select OF
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select OF_EARLY_FLATTREE
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select IRQ_DOMAIN
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select HANDLE_DOMAIN_IRQ
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select GPIOLIB
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select HAVE_ARCH_TRACEHOOK
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select SPARSE_IRQ
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select GENERIC_IRQ_CHIP
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select GENERIC_IRQ_PROBE
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select GENERIC_IRQ_SHOW
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select GENERIC_IOMAP
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select GENERIC_CPU_DEVICES
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select HAVE_UID16
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select GENERIC_ATOMIC64
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select GENERIC_CLOCKEVENTS_BROADCAST
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select GENERIC_STRNCPY_FROM_USER
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select GENERIC_STRNLEN_USER
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select GENERIC_SMP_IDLE_THREAD
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select MODULES_USE_ELF_RELA
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select HAVE_DEBUG_STACKOVERFLOW
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select OR1K_PIC
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select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
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select ARCH_USE_QUEUED_SPINLOCKS
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select ARCH_USE_QUEUED_RWLOCKS
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select OMPIC if SMP
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select ARCH_WANT_FRAME_POINTERS
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select GENERIC_IRQ_MULTI_HANDLER
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select MMU_GATHER_NO_RANGE if MMU
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select SET_FS
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config CPU_BIG_ENDIAN
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def_bool y
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config MMU
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def_bool y
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config GENERIC_HWEIGHT
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def_bool y
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config NO_IOPORT_MAP
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def_bool y
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config TRACE_IRQFLAGS_SUPPORT
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def_bool y
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# For now, use generic checksum functions
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#These can be reimplemented in assembly later if so inclined
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config GENERIC_CSUM
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def_bool y
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config STACKTRACE_SUPPORT
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def_bool y
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config LOCKDEP_SUPPORT
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def_bool y
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menu "Processor type and features"
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choice
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prompt "Subarchitecture"
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default OR1K_1200
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config OR1K_1200
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bool "OR1200"
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help
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Generic OpenRISC 1200 architecture
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endchoice
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config DCACHE_WRITETHROUGH
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bool "Have write through data caches"
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default n
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help
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Select this if your implementation features write through data caches.
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Selecting 'N' here will allow the kernel to force flushing of data
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caches at relevant times. Most OpenRISC implementations support write-
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through data caches.
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If unsure say N here
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config OPENRISC_BUILTIN_DTB
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string "Builtin DTB"
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default ""
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menu "Class II Instructions"
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config OPENRISC_HAVE_INST_FF1
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bool "Have instruction l.ff1"
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default y
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help
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Select this if your implementation has the Class II instruction l.ff1
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config OPENRISC_HAVE_INST_FL1
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bool "Have instruction l.fl1"
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default y
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help
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Select this if your implementation has the Class II instruction l.fl1
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config OPENRISC_HAVE_INST_MUL
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bool "Have instruction l.mul for hardware multiply"
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default y
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help
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Select this if your implementation has a hardware multiply instruction
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config OPENRISC_HAVE_INST_DIV
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bool "Have instruction l.div for hardware divide"
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default y
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help
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Select this if your implementation has a hardware divide instruction
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endmenu
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config NR_CPUS
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int "Maximum number of CPUs (2-32)"
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range 2 32
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depends on SMP
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default "2"
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config SMP
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bool "Symmetric Multi-Processing support"
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help
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This enables support for systems with more than one CPU. If you have
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a system with only one CPU, say N. If you have a system with more
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than one CPU, say Y.
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If you don't know what to do here, say N.
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source "kernel/Kconfig.hz"
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config OPENRISC_NO_SPR_SR_DSX
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bool "use SPR_SR_DSX software emulation" if OR1K_1200
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default y
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help
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SPR_SR_DSX bit is status register bit indicating whether
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the last exception has happened in delay slot.
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OpenRISC architecture makes it optional to have it implemented
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in hardware and the OR1200 does not have it.
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Say N here if you know that your OpenRISC processor has
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SPR_SR_DSX bit implemented. Say Y if you are unsure.
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config OPENRISC_HAVE_SHADOW_GPRS
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bool "Support for shadow gpr files" if !SMP
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default y if SMP
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help
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Say Y here if your OpenRISC processor features shadowed
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register files. They will in such case be used as a
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scratch reg storage on exception entry.
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On SMP systems, this feature is mandatory.
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On a unicore system it's safe to say N here if you are unsure.
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config CMDLINE
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string "Default kernel command string"
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default ""
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help
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On some architectures there is currently no way for the boot loader
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to pass arguments to the kernel. For these architectures, you should
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supply some command-line options at build time by entering them
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here.
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menu "Debugging options"
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config JUMP_UPON_UNHANDLED_EXCEPTION
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bool "Try to die gracefully"
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default y
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help
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Now this puts kernel into infinite loop after first oops. Till
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your kernel crashes this doesn't have any influence.
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Say Y if you are unsure.
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config OPENRISC_ESR_EXCEPTION_BUG_CHECK
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bool "Check for possible ESR exception bug"
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default n
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help
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This option enables some checks that might expose some problems
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in kernel.
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Say N if you are unsure.
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endmenu
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endmenu
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