mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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e58c3495e6
This patch consolidates the variety of macros used for loading 32 or 64-bit constants in assembler (LOADADDR, LOADBASE, SET_REG_TO_*). The idea is to make the set of macros consistent across 32 and 64 bit and to make it more obvious which is the appropriate one to use in a given situation. The new macros and their semantics are described in the comments in ppc_asm.h. In the process, we change several places that were unnecessarily using immediate loads on ppc64 to use the GOT/TOC. Likewise we cleanup a couple of places where we were clumsily subtracting PAGE_OFFSET with asm instructions to use assemble-time arithmetic or the toreal() macro instead. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
950 lines
19 KiB
ArmAsm
950 lines
19 KiB
ArmAsm
/*
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* arch/powerpc/kernel/misc64.S
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*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
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* PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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.text
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/*
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* Returns (address we are running at) - (address we were linked at)
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* for use before the text and data are mapped to KERNELBASE.
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*/
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_GLOBAL(reloc_offset)
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mflr r0
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bl 1f
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1: mflr r3
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LOAD_REG_IMMEDIATE(r4,1b)
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subf r3,r4,r3
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mtlr r0
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blr
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/*
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* add_reloc_offset(x) returns x + reloc_offset().
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*/
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_GLOBAL(add_reloc_offset)
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mflr r0
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bl 1f
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1: mflr r5
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LOAD_REG_IMMEDIATE(r4,1b)
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subf r5,r4,r5
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add r3,r3,r5
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mtlr r0
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blr
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_GLOBAL(get_msr)
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mfmsr r3
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blr
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_GLOBAL(get_dar)
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mfdar r3
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blr
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_GLOBAL(get_srr0)
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mfsrr0 r3
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blr
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_GLOBAL(get_srr1)
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mfsrr1 r3
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blr
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_GLOBAL(get_sp)
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mr r3,r1
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blr
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#ifdef CONFIG_IRQSTACKS
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_GLOBAL(call_do_softirq)
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mflr r0
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std r0,16(r1)
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stdu r1,THREAD_SIZE-112(r3)
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mr r1,r3
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bl .__do_softirq
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ld r1,0(r1)
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ld r0,16(r1)
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mtlr r0
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blr
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_GLOBAL(call___do_IRQ)
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mflr r0
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std r0,16(r1)
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stdu r1,THREAD_SIZE-112(r5)
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mr r1,r5
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bl .__do_IRQ
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ld r1,0(r1)
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ld r0,16(r1)
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mtlr r0
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blr
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#endif /* CONFIG_IRQSTACKS */
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/*
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* To be called by C code which needs to do some operations with MMU
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* disabled. Note that interrupts have to be disabled by the caller
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* prior to calling us. The code called _MUST_ be in the RMO of course
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* and part of the linear mapping as we don't attempt to translate the
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* stack pointer at all. The function is called with the stack switched
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* to this CPU emergency stack
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*
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* prototype is void *call_with_mmu_off(void *func, void *data);
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*
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* the called function is expected to be of the form
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*
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* void *called(void *data);
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*/
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_GLOBAL(call_with_mmu_off)
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mflr r0 /* get link, save it on stackframe */
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std r0,16(r1)
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mr r1,r5 /* save old stack ptr */
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ld r1,PACAEMERGSP(r13) /* get emerg. stack */
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subi r1,r1,STACK_FRAME_OVERHEAD
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std r0,16(r1) /* save link on emerg. stack */
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std r5,0(r1) /* save old stack ptr in backchain */
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ld r3,0(r3) /* get to real function ptr (assume same TOC) */
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bl 2f /* we need LR to return, continue at label 2 */
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ld r0,16(r1) /* we return here from the call, get LR and */
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ld r1,0(r1) /* .. old stack ptr */
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mtspr SPRN_SRR0,r0 /* and get back to virtual mode with these */
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mfmsr r4
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ori r4,r4,MSR_IR|MSR_DR
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mtspr SPRN_SRR1,r4
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rfid
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2: mtspr SPRN_SRR0,r3 /* coming from above, enter real mode */
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mr r3,r4 /* get parameter */
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mfmsr r0
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ori r0,r0,MSR_IR|MSR_DR
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xori r0,r0,MSR_IR|MSR_DR
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mtspr SPRN_SRR1,r0
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rfid
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.section ".toc","aw"
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PPC64_CACHES:
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.tc ppc64_caches[TC],ppc64_caches
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.section ".text"
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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*
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* flush all bytes from start through stop-1 inclusive
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*/
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_KPROBE(__flush_icache_range)
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/*
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* Flush the data cache to memory
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*
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* Different systems have different cache line sizes
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* and in some cases i-cache and d-cache line sizes differ from
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* each other.
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*/
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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1: dcbst 0,r6
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add r6,r6,r7
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bdnz 1b
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sync
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/* Now invalidate the instruction cache */
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lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5
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lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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2: icbi 0,r6
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add r6,r6,r7
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bdnz 2b
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isync
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blr
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.previous .text
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/*
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* Like above, but only do the D-cache.
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*
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* flush_dcache_range(unsigned long start, unsigned long stop)
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*
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* flush all bytes from start to stop-1 inclusive
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*/
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_GLOBAL(flush_dcache_range)
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/*
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* Flush the data cache to memory
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*
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* Different systems have different cache line sizes
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*/
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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0: dcbst 0,r6
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add r6,r6,r7
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bdnz 0b
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sync
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blr
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/*
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* Like above, but works on non-mapped physical addresses.
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* Use only for non-LPAR setups ! It also assumes real mode
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* is cacheable. Used for flushing out the DART before using
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* it as uncacheable memory
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*
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* flush_dcache_phys_range(unsigned long start, unsigned long stop)
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*
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* flush all bytes from start to stop-1 inclusive
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*/
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_GLOBAL(flush_dcache_phys_range)
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mfmsr r5 /* Disable MMU Data Relocation */
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ori r0,r5,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsr r0
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sync
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isync
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mtctr r8
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0: dcbst 0,r6
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add r6,r6,r7
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bdnz 0b
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sync
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isync
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mtmsr r5 /* Re-enable MMU Data Relocation */
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sync
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isync
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blr
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_GLOBAL(flush_inval_dcache_range)
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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sync
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isync
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mtctr r8
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0: dcbf 0,r6
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add r6,r6,r7
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bdnz 0b
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sync
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isync
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blr
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/*
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* Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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*
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* void __flush_dcache_icache(void *page)
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*/
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_GLOBAL(__flush_dcache_icache)
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/*
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* Flush the data cache to memory
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*
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* Different systems have different cache line sizes
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*/
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/* Flush the dcache */
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ld r7,PPC64_CACHES@toc(r2)
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clrrdi r3,r3,PAGE_SHIFT /* Page align */
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lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
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lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
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mr r6,r3
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mtctr r4
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0: dcbst 0,r6
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add r6,r6,r5
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bdnz 0b
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sync
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/* Now invalidate the icache */
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lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
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lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
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mtctr r4
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1: icbi 0,r3
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add r3,r3,r5
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bdnz 1b
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isync
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blr
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/*
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* I/O string operations
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*
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* insb(port, buf, len)
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* outsb(port, buf, len)
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* insw(port, buf, len)
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* outsw(port, buf, len)
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* insl(port, buf, len)
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* outsl(port, buf, len)
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* insw_ns(port, buf, len)
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* outsw_ns(port, buf, len)
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* insl_ns(port, buf, len)
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* outsl_ns(port, buf, len)
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*
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* The *_ns versions don't do byte-swapping.
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*/
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_GLOBAL(_insb)
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cmpwi 0,r5,0
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mtctr r5
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subi r4,r4,1
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blelr-
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00: lbz r5,0(r3)
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eieio
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stbu r5,1(r4)
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bdnz 00b
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twi 0,r5,0
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isync
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blr
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_GLOBAL(_outsb)
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cmpwi 0,r5,0
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mtctr r5
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subi r4,r4,1
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blelr-
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00: lbzu r5,1(r4)
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stb r5,0(r3)
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bdnz 00b
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sync
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blr
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_GLOBAL(_insw)
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cmpwi 0,r5,0
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mtctr r5
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subi r4,r4,2
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blelr-
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00: lhbrx r5,0,r3
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eieio
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sthu r5,2(r4)
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bdnz 00b
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twi 0,r5,0
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isync
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blr
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_GLOBAL(_outsw)
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cmpwi 0,r5,0
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mtctr r5
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subi r4,r4,2
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blelr-
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00: lhzu r5,2(r4)
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sthbrx r5,0,r3
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bdnz 00b
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sync
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blr
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_GLOBAL(_insl)
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cmpwi 0,r5,0
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mtctr r5
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subi r4,r4,4
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blelr-
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00: lwbrx r5,0,r3
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eieio
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stwu r5,4(r4)
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bdnz 00b
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twi 0,r5,0
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isync
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blr
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_GLOBAL(_outsl)
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cmpwi 0,r5,0
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mtctr r5
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subi r4,r4,4
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blelr-
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00: lwzu r5,4(r4)
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stwbrx r5,0,r3
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bdnz 00b
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sync
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blr
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/* _GLOBAL(ide_insw) now in drivers/ide/ide-iops.c */
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_GLOBAL(_insw_ns)
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cmpwi 0,r5,0
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mtctr r5
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subi r4,r4,2
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blelr-
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00: lhz r5,0(r3)
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eieio
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sthu r5,2(r4)
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bdnz 00b
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twi 0,r5,0
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isync
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blr
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/* _GLOBAL(ide_outsw) now in drivers/ide/ide-iops.c */
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_GLOBAL(_outsw_ns)
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cmpwi 0,r5,0
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mtctr r5
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subi r4,r4,2
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blelr-
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00: lhzu r5,2(r4)
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sth r5,0(r3)
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bdnz 00b
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sync
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blr
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_GLOBAL(_insl_ns)
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cmpwi 0,r5,0
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mtctr r5
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subi r4,r4,4
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blelr-
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00: lwz r5,0(r3)
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eieio
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stwu r5,4(r4)
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bdnz 00b
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twi 0,r5,0
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isync
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blr
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_GLOBAL(_outsl_ns)
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cmpwi 0,r5,0
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mtctr r5
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subi r4,r4,4
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blelr-
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00: lwzu r5,4(r4)
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stw r5,0(r3)
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bdnz 00b
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sync
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blr
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/*
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* identify_cpu and calls setup_cpu
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* In: r3 = base of the cpu_specs array
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* r4 = address of cur_cpu_spec
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* r5 = relocation offset
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*/
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_GLOBAL(identify_cpu)
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mfpvr r7
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1:
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lwz r8,CPU_SPEC_PVR_MASK(r3)
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and r8,r8,r7
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lwz r9,CPU_SPEC_PVR_VALUE(r3)
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cmplw 0,r9,r8
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beq 1f
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addi r3,r3,CPU_SPEC_ENTRY_SIZE
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b 1b
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1:
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sub r0,r3,r5
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std r0,0(r4)
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ld r4,CPU_SPEC_SETUP(r3)
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add r4,r4,r5
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ld r4,0(r4)
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add r4,r4,r5
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mtctr r4
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/* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
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mr r4,r3
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mr r3,r5
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bctr
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/*
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* do_cpu_ftr_fixups - goes through the list of CPU feature fixups
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* and writes nop's over sections of code that don't apply for this cpu.
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* r3 = data offset (not changed)
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*/
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_GLOBAL(do_cpu_ftr_fixups)
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/* Get CPU 0 features */
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LOAD_REG_IMMEDIATE(r6,cur_cpu_spec)
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sub r6,r6,r3
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ld r4,0(r6)
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sub r4,r4,r3
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|
ld r4,CPU_SPEC_FEATURES(r4)
|
|
/* Get the fixup table */
|
|
LOAD_REG_IMMEDIATE(r6,__start___ftr_fixup)
|
|
sub r6,r6,r3
|
|
LOAD_REG_IMMEDIATE(r7,__stop___ftr_fixup)
|
|
sub r7,r7,r3
|
|
/* Do the fixup */
|
|
1: cmpld r6,r7
|
|
bgelr
|
|
addi r6,r6,32
|
|
ld r8,-32(r6) /* mask */
|
|
and r8,r8,r4
|
|
ld r9,-24(r6) /* value */
|
|
cmpld r8,r9
|
|
beq 1b
|
|
ld r8,-16(r6) /* section begin */
|
|
ld r9,-8(r6) /* section end */
|
|
subf. r9,r8,r9
|
|
beq 1b
|
|
/* write nops over the section of code */
|
|
/* todo: if large section, add a branch at the start of it */
|
|
srwi r9,r9,2
|
|
mtctr r9
|
|
sub r8,r8,r3
|
|
lis r0,0x60000000@h /* nop */
|
|
3: stw r0,0(r8)
|
|
andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
|
|
beq 2f
|
|
dcbst 0,r8 /* suboptimal, but simpler */
|
|
sync
|
|
icbi 0,r8
|
|
2: addi r8,r8,4
|
|
bdnz 3b
|
|
sync /* additional sync needed on g4 */
|
|
isync
|
|
b 1b
|
|
|
|
#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
|
|
/*
|
|
* Do an IO access in real mode
|
|
*/
|
|
_GLOBAL(real_readb)
|
|
mfmsr r7
|
|
ori r0,r7,MSR_DR
|
|
xori r0,r0,MSR_DR
|
|
sync
|
|
mtmsrd r0
|
|
sync
|
|
isync
|
|
mfspr r6,SPRN_HID4
|
|
rldicl r5,r6,32,0
|
|
ori r5,r5,0x100
|
|
rldicl r5,r5,32,0
|
|
sync
|
|
mtspr SPRN_HID4,r5
|
|
isync
|
|
slbia
|
|
isync
|
|
lbz r3,0(r3)
|
|
sync
|
|
mtspr SPRN_HID4,r6
|
|
isync
|
|
slbia
|
|
isync
|
|
mtmsrd r7
|
|
sync
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Do an IO access in real mode
|
|
*/
|
|
_GLOBAL(real_writeb)
|
|
mfmsr r7
|
|
ori r0,r7,MSR_DR
|
|
xori r0,r0,MSR_DR
|
|
sync
|
|
mtmsrd r0
|
|
sync
|
|
isync
|
|
mfspr r6,SPRN_HID4
|
|
rldicl r5,r6,32,0
|
|
ori r5,r5,0x100
|
|
rldicl r5,r5,32,0
|
|
sync
|
|
mtspr SPRN_HID4,r5
|
|
isync
|
|
slbia
|
|
isync
|
|
stb r3,0(r4)
|
|
sync
|
|
mtspr SPRN_HID4,r6
|
|
isync
|
|
slbia
|
|
isync
|
|
mtmsrd r7
|
|
sync
|
|
isync
|
|
blr
|
|
#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
|
|
|
|
/*
|
|
* SCOM access functions for 970 (FX only for now)
|
|
*
|
|
* unsigned long scom970_read(unsigned int address);
|
|
* void scom970_write(unsigned int address, unsigned long value);
|
|
*
|
|
* The address passed in is the 24 bits register address. This code
|
|
* is 970 specific and will not check the status bits, so you should
|
|
* know what you are doing.
|
|
*/
|
|
_GLOBAL(scom970_read)
|
|
/* interrupts off */
|
|
mfmsr r4
|
|
ori r0,r4,MSR_EE
|
|
xori r0,r0,MSR_EE
|
|
mtmsrd r0,1
|
|
|
|
/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
|
|
* (including parity). On current CPUs they must be 0'd,
|
|
* and finally or in RW bit
|
|
*/
|
|
rlwinm r3,r3,8,0,15
|
|
ori r3,r3,0x8000
|
|
|
|
/* do the actual scom read */
|
|
sync
|
|
mtspr SPRN_SCOMC,r3
|
|
isync
|
|
mfspr r3,SPRN_SCOMD
|
|
isync
|
|
mfspr r0,SPRN_SCOMC
|
|
isync
|
|
|
|
/* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
|
|
* that's the best we can do). Not implemented yet as we don't use
|
|
* the scom on any of the bogus CPUs yet, but may have to be done
|
|
* ultimately
|
|
*/
|
|
|
|
/* restore interrupts */
|
|
mtmsrd r4,1
|
|
blr
|
|
|
|
|
|
_GLOBAL(scom970_write)
|
|
/* interrupts off */
|
|
mfmsr r5
|
|
ori r0,r5,MSR_EE
|
|
xori r0,r0,MSR_EE
|
|
mtmsrd r0,1
|
|
|
|
/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
|
|
* (including parity). On current CPUs they must be 0'd.
|
|
*/
|
|
|
|
rlwinm r3,r3,8,0,15
|
|
|
|
sync
|
|
mtspr SPRN_SCOMD,r4 /* write data */
|
|
isync
|
|
mtspr SPRN_SCOMC,r3 /* write command */
|
|
isync
|
|
mfspr 3,SPRN_SCOMC
|
|
isync
|
|
|
|
/* restore interrupts */
|
|
mtmsrd r5,1
|
|
blr
|
|
|
|
|
|
/*
|
|
* Create a kernel thread
|
|
* kernel_thread(fn, arg, flags)
|
|
*/
|
|
_GLOBAL(kernel_thread)
|
|
std r29,-24(r1)
|
|
std r30,-16(r1)
|
|
stdu r1,-STACK_FRAME_OVERHEAD(r1)
|
|
mr r29,r3
|
|
mr r30,r4
|
|
ori r3,r5,CLONE_VM /* flags */
|
|
oris r3,r3,(CLONE_UNTRACED>>16)
|
|
li r4,0 /* new sp (unused) */
|
|
li r0,__NR_clone
|
|
sc
|
|
cmpdi 0,r3,0 /* parent or child? */
|
|
bne 1f /* return if parent */
|
|
li r0,0
|
|
stdu r0,-STACK_FRAME_OVERHEAD(r1)
|
|
ld r2,8(r29)
|
|
ld r29,0(r29)
|
|
mtlr r29 /* fn addr in lr */
|
|
mr r3,r30 /* load arg and call fn */
|
|
blrl
|
|
li r0,__NR_exit /* exit after child exits */
|
|
li r3,0
|
|
sc
|
|
1: addi r1,r1,STACK_FRAME_OVERHEAD
|
|
ld r29,-24(r1)
|
|
ld r30,-16(r1)
|
|
blr
|
|
|
|
/*
|
|
* disable_kernel_fp()
|
|
* Disable the FPU.
|
|
*/
|
|
_GLOBAL(disable_kernel_fp)
|
|
mfmsr r3
|
|
rldicl r0,r3,(63-MSR_FP_LG),1
|
|
rldicl r3,r0,(MSR_FP_LG+1),0
|
|
mtmsrd r3 /* disable use of fpu now */
|
|
isync
|
|
blr
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
#if 0 /* this has no callers for now */
|
|
/*
|
|
* disable_kernel_altivec()
|
|
* Disable the VMX.
|
|
*/
|
|
_GLOBAL(disable_kernel_altivec)
|
|
mfmsr r3
|
|
rldicl r0,r3,(63-MSR_VEC_LG),1
|
|
rldicl r3,r0,(MSR_VEC_LG+1),0
|
|
mtmsrd r3 /* disable use of VMX now */
|
|
isync
|
|
blr
|
|
#endif /* 0 */
|
|
|
|
/*
|
|
* giveup_altivec(tsk)
|
|
* Disable VMX for the task given as the argument,
|
|
* and save the vector registers in its thread_struct.
|
|
* Enables the VMX for use in the kernel on return.
|
|
*/
|
|
_GLOBAL(giveup_altivec)
|
|
mfmsr r5
|
|
oris r5,r5,MSR_VEC@h
|
|
mtmsrd r5 /* enable use of VMX now */
|
|
isync
|
|
cmpdi 0,r3,0
|
|
beqlr- /* if no previous owner, done */
|
|
addi r3,r3,THREAD /* want THREAD of task */
|
|
ld r5,PT_REGS(r3)
|
|
cmpdi 0,r5,0
|
|
SAVE_32VRS(0,r4,r3)
|
|
mfvscr vr0
|
|
li r4,THREAD_VSCR
|
|
stvx vr0,r4,r3
|
|
beq 1f
|
|
ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
|
|
lis r3,MSR_VEC@h
|
|
andc r4,r4,r3 /* disable FP for previous task */
|
|
std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
|
|
1:
|
|
#ifndef CONFIG_SMP
|
|
li r5,0
|
|
ld r4,last_task_used_altivec@got(r2)
|
|
std r5,0(r4)
|
|
#endif /* CONFIG_SMP */
|
|
blr
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
|
|
|
_GLOBAL(__setup_cpu_power3)
|
|
blr
|
|
|
|
_GLOBAL(execve)
|
|
li r0,__NR_execve
|
|
sc
|
|
bnslr
|
|
neg r3,r3
|
|
blr
|
|
|
|
/* kexec_wait(phys_cpu)
|
|
*
|
|
* wait for the flag to change, indicating this kernel is going away but
|
|
* the slave code for the next one is at addresses 0 to 100.
|
|
*
|
|
* This is used by all slaves.
|
|
*
|
|
* Physical (hardware) cpu id should be in r3.
|
|
*/
|
|
_GLOBAL(kexec_wait)
|
|
bl 1f
|
|
1: mflr r5
|
|
addi r5,r5,kexec_flag-1b
|
|
|
|
99: HMT_LOW
|
|
#ifdef CONFIG_KEXEC /* use no memory without kexec */
|
|
lwz r4,0(r5)
|
|
cmpwi 0,r4,0
|
|
bnea 0x60
|
|
#endif
|
|
b 99b
|
|
|
|
/* this can be in text because we won't change it until we are
|
|
* running in real anyways
|
|
*/
|
|
kexec_flag:
|
|
.long 0
|
|
|
|
|
|
#ifdef CONFIG_KEXEC
|
|
|
|
/* kexec_smp_wait(void)
|
|
*
|
|
* call with interrupts off
|
|
* note: this is a terminal routine, it does not save lr
|
|
*
|
|
* get phys id from paca
|
|
* set paca id to -1 to say we got here
|
|
* switch to real mode
|
|
* join other cpus in kexec_wait(phys_id)
|
|
*/
|
|
_GLOBAL(kexec_smp_wait)
|
|
lhz r3,PACAHWCPUID(r13)
|
|
li r4,-1
|
|
sth r4,PACAHWCPUID(r13) /* let others know we left */
|
|
bl real_mode
|
|
b .kexec_wait
|
|
|
|
/*
|
|
* switch to real mode (turn mmu off)
|
|
* we use the early kernel trick that the hardware ignores bits
|
|
* 0 and 1 (big endian) of the effective address in real mode
|
|
*
|
|
* don't overwrite r3 here, it is live for kexec_wait above.
|
|
*/
|
|
real_mode: /* assume normal blr return */
|
|
1: li r9,MSR_RI
|
|
li r10,MSR_DR|MSR_IR
|
|
mflr r11 /* return address to SRR0 */
|
|
mfmsr r12
|
|
andc r9,r12,r9
|
|
andc r10,r12,r10
|
|
|
|
mtmsrd r9,1
|
|
mtspr SPRN_SRR1,r10
|
|
mtspr SPRN_SRR0,r11
|
|
rfid
|
|
|
|
|
|
/*
|
|
* kexec_sequence(newstack, start, image, control, clear_all())
|
|
*
|
|
* does the grungy work with stack switching and real mode switches
|
|
* also does simple calls to other code
|
|
*/
|
|
|
|
_GLOBAL(kexec_sequence)
|
|
mflr r0
|
|
std r0,16(r1)
|
|
|
|
/* switch stacks to newstack -- &kexec_stack.stack */
|
|
stdu r1,THREAD_SIZE-112(r3)
|
|
mr r1,r3
|
|
|
|
li r0,0
|
|
std r0,16(r1)
|
|
|
|
/* save regs for local vars on new stack.
|
|
* yes, we won't go back, but ...
|
|
*/
|
|
std r31,-8(r1)
|
|
std r30,-16(r1)
|
|
std r29,-24(r1)
|
|
std r28,-32(r1)
|
|
std r27,-40(r1)
|
|
std r26,-48(r1)
|
|
std r25,-56(r1)
|
|
|
|
stdu r1,-112-64(r1)
|
|
|
|
/* save args into preserved regs */
|
|
mr r31,r3 /* newstack (both) */
|
|
mr r30,r4 /* start (real) */
|
|
mr r29,r5 /* image (virt) */
|
|
mr r28,r6 /* control, unused */
|
|
mr r27,r7 /* clear_all() fn desc */
|
|
mr r26,r8 /* spare */
|
|
lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
|
|
|
|
/* disable interrupts, we are overwriting kernel data next */
|
|
mfmsr r3
|
|
rlwinm r3,r3,0,17,15
|
|
mtmsrd r3,1
|
|
|
|
/* copy dest pages, flush whole dest image */
|
|
mr r3,r29
|
|
bl .kexec_copy_flush /* (image) */
|
|
|
|
/* turn off mmu */
|
|
bl real_mode
|
|
|
|
/* clear out hardware hash page table and tlb */
|
|
ld r5,0(r27) /* deref function descriptor */
|
|
mtctr r5
|
|
bctrl /* ppc_md.hash_clear_all(void); */
|
|
|
|
/*
|
|
* kexec image calling is:
|
|
* the first 0x100 bytes of the entry point are copied to 0
|
|
*
|
|
* all slaves branch to slave = 0x60 (absolute)
|
|
* slave(phys_cpu_id);
|
|
*
|
|
* master goes to start = entry point
|
|
* start(phys_cpu_id, start, 0);
|
|
*
|
|
*
|
|
* a wrapper is needed to call existing kernels, here is an approximate
|
|
* description of one method:
|
|
*
|
|
* v2: (2.6.10)
|
|
* start will be near the boot_block (maybe 0x100 bytes before it?)
|
|
* it will have a 0x60, which will b to boot_block, where it will wait
|
|
* and 0 will store phys into struct boot-block and load r3 from there,
|
|
* copy kernel 0-0x100 and tell slaves to back down to 0x60 again
|
|
*
|
|
* v1: (2.6.9)
|
|
* boot block will have all cpus scanning device tree to see if they
|
|
* are the boot cpu ?????
|
|
* other device tree differences (prop sizes, va vs pa, etc)...
|
|
*/
|
|
|
|
/* copy 0x100 bytes starting at start to 0 */
|
|
li r3,0
|
|
mr r4,r30
|
|
li r5,0x100
|
|
li r6,0
|
|
bl .copy_and_flush /* (dest, src, copy limit, start offset) */
|
|
1: /* assume normal blr return */
|
|
|
|
/* release other cpus to the new kernel secondary start at 0x60 */
|
|
mflr r5
|
|
li r6,1
|
|
stw r6,kexec_flag-1b(5)
|
|
mr r3,r25 # my phys cpu
|
|
mr r4,r30 # start, aka phys mem offset
|
|
mtlr 4
|
|
li r5,0
|
|
blr /* image->start(physid, image->start, 0); */
|
|
#endif /* CONFIG_KEXEC */
|