Palmer Dabbelt c901e45a99 RISC-V: sfence.vma orderes the instruction cache ... This is just a comment change, but it's one that bit me on the mailing list. It turns out that issuing a `sfence.vma` enforces instruction cache ordering in addition to TLB ordering. This isn't explicitly called out in the ISA manual, but Andrew will be making that more clear in a future revision. CC: Andrew Waterman <andrew@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2017-11-28 14:06:17 -08:00
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configs	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00
include	RISC-V: sfence.vma orderes the instruction cache	2017-11-28 14:06:17 -08:00
kernel	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00
lib	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00
mm	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00
Kconfig	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00
Makefile	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00