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![Alexander Clouter](/assets/img/avatar_default.png)
Received official word finally from Technological Systems on which FPGA ID's they have released unto the world. Also an additional of a dummy entry matching the FPGA ID of the Verilog template on our wiki. Signed-off-by: Alexander Clouter <alex@digriz.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
501 lines
12 KiB
C
501 lines
12 KiB
C
/*
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* arch/arm/mach-orion5x/ts78xx-setup.c
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*
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* Maintainer: Alexander Clouter <alex@digriz.org.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sysfs.h>
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#include <linux/platform_device.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ata_platform.h>
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#include <linux/m48t86.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/orion5x.h>
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#include "common.h"
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#include "mpp.h"
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#include "ts78xx-fpga.h"
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/*****************************************************************************
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* TS-78xx Info
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****************************************************************************/
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/*
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* FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
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*/
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#define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
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#define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000
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#define TS78XX_FPGA_REGS_SIZE SZ_1M
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static struct ts78xx_fpga_data ts78xx_fpga = {
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.id = 0,
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.state = 1,
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/* .supports = ... - populated by ts78xx_fpga_supports() */
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};
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc ts78xx_io_desc[] __initdata = {
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{
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.virtual = TS78XX_FPGA_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
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.length = TS78XX_FPGA_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init ts78xx_map_io(void)
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{
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orion5x_map_io();
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iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
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}
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/*****************************************************************************
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* Ethernet
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****************************************************************************/
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static struct mv643xx_eth_platform_data ts78xx_eth_data = {
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.phy_addr = MV643XX_ETH_PHY_ADDR(0),
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};
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/*****************************************************************************
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* SATA
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****************************************************************************/
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static struct mv_sata_platform_data ts78xx_sata_data = {
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.n_ports = 2,
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};
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/*****************************************************************************
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* RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
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****************************************************************************/
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#define TS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
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#define TS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
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static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr)
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{
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writeb(addr, TS_RTC_CTRL);
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return readb(TS_RTC_DATA);
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}
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static void ts78xx_ts_rtc_writebyte(unsigned char value, unsigned long addr)
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{
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writeb(addr, TS_RTC_CTRL);
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writeb(value, TS_RTC_DATA);
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}
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static struct m48t86_ops ts78xx_ts_rtc_ops = {
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.readbyte = ts78xx_ts_rtc_readbyte,
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.writebyte = ts78xx_ts_rtc_writebyte,
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};
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static struct platform_device ts78xx_ts_rtc_device = {
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.name = "rtc-m48t86",
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.id = -1,
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.dev = {
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.platform_data = &ts78xx_ts_rtc_ops,
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},
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.num_resources = 0,
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};
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/*
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* TS uses some of the user storage space on the RTC chip so see if it is
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* present; as it's an optional feature at purchase time and not all boards
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* will have it present
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*
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* I've used the method TS use in their rtc7800.c example for the detection
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*
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* TODO: track down a guinea pig without an RTC to see if we can work out a
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* better RTC detection routine
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*/
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static int ts78xx_ts_rtc_load(void)
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{
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int rc;
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unsigned char tmp_rtc0, tmp_rtc1;
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tmp_rtc0 = ts78xx_ts_rtc_readbyte(126);
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tmp_rtc1 = ts78xx_ts_rtc_readbyte(127);
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ts78xx_ts_rtc_writebyte(0x00, 126);
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ts78xx_ts_rtc_writebyte(0x55, 127);
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if (ts78xx_ts_rtc_readbyte(127) == 0x55) {
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ts78xx_ts_rtc_writebyte(0xaa, 127);
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if (ts78xx_ts_rtc_readbyte(127) == 0xaa
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&& ts78xx_ts_rtc_readbyte(126) == 0x00) {
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ts78xx_ts_rtc_writebyte(tmp_rtc0, 126);
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ts78xx_ts_rtc_writebyte(tmp_rtc1, 127);
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if (ts78xx_fpga.supports.ts_rtc.init == 0) {
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rc = platform_device_register(&ts78xx_ts_rtc_device);
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if (!rc)
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ts78xx_fpga.supports.ts_rtc.init = 1;
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} else
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rc = platform_device_add(&ts78xx_ts_rtc_device);
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return rc;
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}
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}
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return -ENODEV;
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};
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static void ts78xx_ts_rtc_unload(void)
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{
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platform_device_del(&ts78xx_ts_rtc_device);
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}
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/*****************************************************************************
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* NAND Flash
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****************************************************************************/
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#define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x800) /* VIRT */
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#define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x804) /* PHYS */
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/*
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* hardware specific access to control-lines
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*
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* ctrl:
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* NAND_NCE: bit 0 -> bit 2
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* NAND_CLE: bit 1 -> bit 1
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* NAND_ALE: bit 2 -> bit 0
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*/
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static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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unsigned char bits;
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bits = (ctrl & NAND_NCE) << 2;
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bits |= ctrl & NAND_CLE;
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bits |= (ctrl & NAND_ALE) >> 2;
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writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
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{
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return readb(TS_NAND_CTRL) & 0x20;
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}
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const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
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static struct mtd_partition ts78xx_ts_nand_parts[] = {
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{
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.name = "mbr",
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.offset = 0,
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.size = SZ_128K,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "kernel",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_4M,
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}, {
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.name = "initrd",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_4M,
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}, {
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.name = "rootfs",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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}
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};
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static struct platform_nand_data ts78xx_ts_nand_data = {
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.chip = {
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.part_probe_types = ts_nand_part_probes,
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.partitions = ts78xx_ts_nand_parts,
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.nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts),
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.chip_delay = 15,
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.options = NAND_USE_FLASH_BBT,
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},
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.ctrl = {
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/*
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* The HW ECC offloading functions, used to give about a 9%
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* performance increase for 'dd if=/dev/mtdblockX' and 5% for
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* nanddump. This all however was changed by git commit
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* e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
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* no performance advantage to be had so we no longer bother
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*/
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.cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
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.dev_ready = ts78xx_ts_nand_dev_ready,
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},
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};
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static struct resource ts78xx_ts_nand_resources = {
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.start = TS_NAND_DATA,
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.end = TS_NAND_DATA + 4,
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.flags = IORESOURCE_IO,
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};
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static struct platform_device ts78xx_ts_nand_device = {
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.name = "gen_nand",
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.id = -1,
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.dev = {
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.platform_data = &ts78xx_ts_nand_data,
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},
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.resource = &ts78xx_ts_nand_resources,
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.num_resources = 1,
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};
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static int ts78xx_ts_nand_load(void)
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{
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int rc;
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if (ts78xx_fpga.supports.ts_nand.init == 0) {
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rc = platform_device_register(&ts78xx_ts_nand_device);
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if (!rc)
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ts78xx_fpga.supports.ts_nand.init = 1;
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} else
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rc = platform_device_add(&ts78xx_ts_nand_device);
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return rc;
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};
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static void ts78xx_ts_nand_unload(void)
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{
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platform_device_del(&ts78xx_ts_nand_device);
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}
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/*****************************************************************************
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* FPGA 'hotplug' support code
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****************************************************************************/
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static void ts78xx_fpga_devices_zero_init(void)
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{
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ts78xx_fpga.supports.ts_rtc.init = 0;
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ts78xx_fpga.supports.ts_nand.init = 0;
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}
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static void ts78xx_fpga_supports(void)
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{
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/* TODO: put this 'table' into ts78xx-fpga.h */
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switch (ts78xx_fpga.id) {
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case TS7800_REV_1:
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case TS7800_REV_2:
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case TS7800_REV_3:
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case TS7800_REV_4:
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case TS7800_REV_5:
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ts78xx_fpga.supports.ts_rtc.present = 1;
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ts78xx_fpga.supports.ts_nand.present = 1;
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break;
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default:
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ts78xx_fpga.supports.ts_rtc.present = 0;
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ts78xx_fpga.supports.ts_nand.present = 0;
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}
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}
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static int ts78xx_fpga_load_devices(void)
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{
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int tmp, ret = 0;
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if (ts78xx_fpga.supports.ts_rtc.present == 1) {
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tmp = ts78xx_ts_rtc_load();
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if (tmp) {
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printk(KERN_INFO "TS-78xx: RTC not registered\n");
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ts78xx_fpga.supports.ts_rtc.present = 0;
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}
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ret |= tmp;
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}
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if (ts78xx_fpga.supports.ts_nand.present == 1) {
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tmp = ts78xx_ts_nand_load();
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if (tmp) {
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printk(KERN_INFO "TS-78xx: NAND not registered\n");
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ts78xx_fpga.supports.ts_nand.present = 0;
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}
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ret |= tmp;
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}
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return ret;
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}
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static int ts78xx_fpga_unload_devices(void)
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{
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int ret = 0;
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if (ts78xx_fpga.supports.ts_rtc.present == 1)
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ts78xx_ts_rtc_unload();
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if (ts78xx_fpga.supports.ts_nand.present == 1)
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ts78xx_ts_nand_unload();
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return ret;
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}
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static int ts78xx_fpga_load(void)
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{
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ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
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printk(KERN_INFO "TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n",
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(ts78xx_fpga.id >> 8) & 0xffffff,
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ts78xx_fpga.id & 0xff);
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ts78xx_fpga_supports();
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if (ts78xx_fpga_load_devices()) {
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ts78xx_fpga.state = -1;
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return -EBUSY;
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}
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return 0;
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};
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static int ts78xx_fpga_unload(void)
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{
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unsigned int fpga_id;
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fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
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/*
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* There does not seem to be a feasible way to block access to the GPIO
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* pins from userspace (/dev/mem). This if clause should hopefully warn
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* those foolish enough not to follow 'policy' :)
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*
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* UrJTAG SVN since r1381 can be used to reprogram the FPGA
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*/
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if (ts78xx_fpga.id != fpga_id) {
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printk(KERN_ERR "TS-78xx FPGA: magic/rev mismatch\n"
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"TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
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(ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
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(fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
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ts78xx_fpga.state = -1;
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return -EBUSY;
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}
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if (ts78xx_fpga_unload_devices()) {
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ts78xx_fpga.state = -1;
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return -EBUSY;
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}
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return 0;
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};
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static ssize_t ts78xx_fpga_show(struct kobject *kobj,
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struct kobj_attribute *attr, char *buf)
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{
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if (ts78xx_fpga.state < 0)
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return sprintf(buf, "borked\n");
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return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
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}
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static ssize_t ts78xx_fpga_store(struct kobject *kobj,
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struct kobj_attribute *attr, const char *buf, size_t n)
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{
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int value, ret;
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if (ts78xx_fpga.state < 0) {
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printk(KERN_ERR "TS-78xx FPGA: borked, you must powercycle asap\n");
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return -EBUSY;
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}
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if (strncmp(buf, "online", sizeof("online") - 1) == 0)
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value = 1;
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else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
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value = 0;
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else {
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printk(KERN_ERR "ts78xx_fpga_store: Invalid value\n");
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return -EINVAL;
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}
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if (ts78xx_fpga.state == value)
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return n;
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ret = (ts78xx_fpga.state == 0)
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? ts78xx_fpga_load()
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: ts78xx_fpga_unload();
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if (!(ret < 0))
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ts78xx_fpga.state = value;
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return n;
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}
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static struct kobj_attribute ts78xx_fpga_attr =
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__ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
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/*****************************************************************************
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* General Setup
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****************************************************************************/
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static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
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{ 0, MPP_UNUSED },
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{ 1, MPP_GPIO }, /* JTAG Clock */
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{ 2, MPP_GPIO }, /* JTAG Data In */
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{ 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */
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{ 4, MPP_GPIO }, /* JTAG Data Out */
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{ 5, MPP_GPIO }, /* JTAG TMS */
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{ 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
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{ 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */
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{ 8, MPP_UNUSED },
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{ 9, MPP_UNUSED },
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{ 10, MPP_UNUSED },
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{ 11, MPP_UNUSED },
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{ 12, MPP_UNUSED },
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{ 13, MPP_UNUSED },
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{ 14, MPP_UNUSED },
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{ 15, MPP_UNUSED },
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{ 16, MPP_UART },
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{ 17, MPP_UART },
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{ 18, MPP_UART },
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{ 19, MPP_UART },
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/*
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* MPP[20] PCI Clock Out 1
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* MPP[21] PCI Clock Out 0
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* MPP[22] Unused
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* MPP[23] Unused
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* MPP[24] Unused
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* MPP[25] Unused
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*/
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{ -1 },
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};
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static void __init ts78xx_init(void)
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{
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int ret;
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/*
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* Setup basic Orion functions. Need to be called early.
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*/
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orion5x_init();
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orion5x_mpp_conf(ts78xx_mpp_modes);
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/*
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* Configure peripherals.
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*/
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orion5x_ehci0_init();
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orion5x_ehci1_init();
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orion5x_eth_init(&ts78xx_eth_data);
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orion5x_sata_init(&ts78xx_sata_data);
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orion5x_uart0_init();
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orion5x_uart1_init();
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orion5x_xor_init();
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/* FPGA init */
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ts78xx_fpga_devices_zero_init();
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ret = ts78xx_fpga_load();
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ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr);
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if (ret)
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printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
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}
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MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
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/* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
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.phys_io = ORION5X_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.init_machine = ts78xx_init,
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.map_io = ts78xx_map_io,
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.init_irq = orion5x_init_irq,
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.timer = &orion5x_timer,
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MACHINE_END
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