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993 lines
20 KiB
C
993 lines
20 KiB
C
/*
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* arch/arm/mach-pnx4008/clock.c
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*
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* Clock control driver for PNX4008
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*
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* Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
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* Generic clock management functions are partially based on:
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* linux/arch/arm/mach-omap/clock.c
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*
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* 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/clock.h>
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#include "clock.h"
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/*forward declaration*/
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static struct clk per_ck;
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static struct clk hclk_ck;
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static struct clk ck_1MHz;
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static struct clk ck_13MHz;
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static struct clk ck_pll1;
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static int local_set_rate(struct clk *clk, u32 rate);
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static inline void clock_lock(void)
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{
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local_irq_disable();
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}
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static inline void clock_unlock(void)
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{
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local_irq_enable();
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}
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static void propagate_rate(struct clk *clk)
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{
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struct clk *tmp_clk;
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tmp_clk = clk;
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while (tmp_clk->propagate_next) {
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tmp_clk = tmp_clk->propagate_next;
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local_set_rate(tmp_clk, tmp_clk->user_rate);
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}
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}
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static inline void clk_reg_disable(struct clk *clk)
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{
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if (clk->enable_reg)
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__raw_writel(__raw_readl(clk->enable_reg) &
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~(1 << clk->enable_shift), clk->enable_reg);
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}
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static inline void clk_reg_enable(struct clk *clk)
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{
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if (clk->enable_reg)
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__raw_writel(__raw_readl(clk->enable_reg) |
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(1 << clk->enable_shift), clk->enable_reg);
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}
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static inline void clk_reg_disable1(struct clk *clk)
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{
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if (clk->enable_reg1)
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__raw_writel(__raw_readl(clk->enable_reg1) &
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~(1 << clk->enable_shift1), clk->enable_reg1);
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}
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static inline void clk_reg_enable1(struct clk *clk)
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{
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if (clk->enable_reg1)
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__raw_writel(__raw_readl(clk->enable_reg1) |
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(1 << clk->enable_shift1), clk->enable_reg1);
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}
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static int clk_wait_for_pll_lock(struct clk *clk)
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{
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int i;
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i = 0;
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while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ; /*wait for PLL to lock */
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if (!(__raw_readl(clk->scale_reg) & 1)) {
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printk(KERN_ERR
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"%s ERROR: failed to lock, scale reg data: %x\n",
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clk->name, __raw_readl(clk->scale_reg));
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return -1;
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}
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return 0;
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}
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static int switch_to_dirty_13mhz(struct clk *clk)
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{
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int i;
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int ret;
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u32 tmp_reg;
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ret = 0;
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if (!clk->rate)
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clk_reg_enable1(clk);
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tmp_reg = __raw_readl(clk->parent_switch_reg);
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/*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
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if (!(tmp_reg & 1)) {
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tmp_reg |= (1 << 1); /* Trigger switch to 13'MHz (dirty) clock */
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__raw_writel(tmp_reg, clk->parent_switch_reg);
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i = 0;
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while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13'MHz selection status */
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if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
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printk(KERN_ERR
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"%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
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clk->name, __raw_readl(clk->parent_switch_reg));
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ret = -1;
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}
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}
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if (!clk->rate)
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clk_reg_disable1(clk);
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return ret;
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}
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static int switch_to_clean_13mhz(struct clk *clk)
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{
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int i;
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int ret;
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u32 tmp_reg;
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ret = 0;
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if (!clk->rate)
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clk_reg_enable1(clk);
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tmp_reg = __raw_readl(clk->parent_switch_reg);
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/*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
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if (tmp_reg & 1) {
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tmp_reg &= ~(1 << 1); /* Trigger switch to 13MHz (clean) clock */
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__raw_writel(tmp_reg, clk->parent_switch_reg);
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i = 0;
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while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13MHz selection status */
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if (__raw_readl(clk->parent_switch_reg) & 1) {
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printk(KERN_ERR
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"%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
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clk->name, __raw_readl(clk->parent_switch_reg));
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ret = -1;
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}
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}
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if (!clk->rate)
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clk_reg_disable1(clk);
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return ret;
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}
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static int set_13MHz_parent(struct clk *clk, struct clk *parent)
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{
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int ret = -EINVAL;
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if (parent == &ck_13MHz)
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ret = switch_to_clean_13mhz(clk);
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else if (parent == &ck_pll1)
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ret = switch_to_dirty_13mhz(clk);
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return ret;
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}
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#define PLL160_MIN_FCCO 156000
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#define PLL160_MAX_FCCO 320000
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/*
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* Calculate pll160 settings.
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* Possible input: up to 320MHz with step of clk->parent->rate.
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* In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
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* Ignored paths: "feedback" (bit 13 set), "div-by-N".
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* Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
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* Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
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* Please refer to PNX4008 IC manual for details.
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*/
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static int pll160_set_rate(struct clk *clk, u32 rate)
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{
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u32 tmp_reg, tmp_m, tmp_2p, i;
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u32 parent_rate;
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int ret = -EINVAL;
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parent_rate = clk->parent->rate;
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if (!parent_rate)
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goto out;
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/* set direct run for ARM or disable output for others */
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clk_reg_disable(clk);
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/* disable source input as well (ignored for ARM) */
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clk_reg_disable1(clk);
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tmp_reg = __raw_readl(clk->scale_reg);
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tmp_reg &= ~0x1ffff; /*clear all settings, power down */
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__raw_writel(tmp_reg, clk->scale_reg);
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rate -= rate % parent_rate; /*round down the input */
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if (rate > PLL160_MAX_FCCO)
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rate = PLL160_MAX_FCCO;
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if (!rate) {
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clk->rate = 0;
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ret = 0;
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goto out;
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}
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clk_reg_enable1(clk);
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tmp_reg = __raw_readl(clk->scale_reg);
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if (rate == parent_rate) {
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/*enter direct bypass mode */
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tmp_reg |= ((1 << 14) | (1 << 15));
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__raw_writel(tmp_reg, clk->scale_reg);
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clk->rate = parent_rate;
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clk_reg_enable(clk);
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ret = 0;
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goto out;
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}
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i = 0;
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for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
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if (rate * tmp_2p >= PLL160_MIN_FCCO)
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break;
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i++;
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}
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if (tmp_2p > 1)
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tmp_reg |= ((i - 1) << 11);
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else
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tmp_reg |= (1 << 14); /*direct mode, no divide */
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tmp_m = rate * tmp_2p;
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tmp_m /= parent_rate;
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tmp_reg |= (tmp_m - 1) << 1; /*calculate M */
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tmp_reg |= (1 << 16); /*power up PLL */
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__raw_writel(tmp_reg, clk->scale_reg);
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if (clk_wait_for_pll_lock(clk) < 0) {
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clk_reg_disable(clk);
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clk_reg_disable1(clk);
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tmp_reg = __raw_readl(clk->scale_reg);
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tmp_reg &= ~0x1ffff; /*clear all settings, power down */
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__raw_writel(tmp_reg, clk->scale_reg);
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clk->rate = 0;
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ret = -EFAULT;
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goto out;
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}
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clk->rate = (tmp_m * parent_rate) / tmp_2p;
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if (clk->flags & RATE_PROPAGATES)
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propagate_rate(clk);
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clk_reg_enable(clk);
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ret = 0;
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out:
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return ret;
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}
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/*configure PER_CLK*/
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static int per_clk_set_rate(struct clk *clk, u32 rate)
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{
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u32 tmp;
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tmp = __raw_readl(clk->scale_reg);
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tmp &= ~(0x1f << 2);
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tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
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__raw_writel(tmp, clk->scale_reg);
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clk->rate = rate;
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return 0;
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}
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/*configure HCLK*/
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static int hclk_set_rate(struct clk *clk, u32 rate)
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{
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u32 tmp;
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tmp = __raw_readl(clk->scale_reg);
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tmp = tmp & ~0x3;
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switch (rate) {
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case 1:
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break;
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case 2:
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tmp |= 1;
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break;
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case 4:
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tmp |= 2;
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break;
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}
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__raw_writel(tmp, clk->scale_reg);
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clk->rate = rate;
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return 0;
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}
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static u32 hclk_round_rate(struct clk *clk, u32 rate)
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{
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switch (rate) {
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case 1:
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case 4:
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return rate;
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}
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return 2;
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}
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static u32 per_clk_round_rate(struct clk *clk, u32 rate)
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{
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return CLK_RATE_13MHZ;
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}
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static int on_off_set_rate(struct clk *clk, u32 rate)
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{
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if (rate) {
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clk_reg_enable(clk);
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clk->rate = 1;
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} else {
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clk_reg_disable(clk);
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clk->rate = 0;
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}
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return 0;
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}
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static int on_off_inv_set_rate(struct clk *clk, u32 rate)
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{
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if (rate) {
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clk_reg_disable(clk); /*enable bit is inverted */
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clk->rate = 1;
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} else {
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clk_reg_enable(clk);
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clk->rate = 0;
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}
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return 0;
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}
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static u32 on_off_round_rate(struct clk *clk, u32 rate)
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{
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return (rate ? 1 : 0);
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}
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static u32 pll4_round_rate(struct clk *clk, u32 rate)
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{
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if (rate > CLK_RATE_208MHZ)
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rate = CLK_RATE_208MHZ;
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if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
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rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
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return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
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}
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static u32 pll3_round_rate(struct clk *clk, u32 rate)
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{
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if (rate > CLK_RATE_208MHZ)
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rate = CLK_RATE_208MHZ;
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return (rate - rate % CLK_RATE_13MHZ);
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}
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static u32 pll5_round_rate(struct clk *clk, u32 rate)
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{
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return (rate ? CLK_RATE_48MHZ : 0);
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}
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static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
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{
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return (rate ? CLK_RATE_13MHZ : 0);
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}
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static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
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{
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if (rate) {
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clk_reg_disable(clk); /*enable bit is inverted */
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udelay(500);
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clk->rate = CLK_RATE_13MHZ;
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ck_1MHz.rate = CLK_RATE_1MHZ;
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} else {
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clk_reg_enable(clk);
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clk->rate = 0;
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ck_1MHz.rate = 0;
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}
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return 0;
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}
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static int pll1_set_rate(struct clk *clk, u32 rate)
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{
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#if 0 /* doesn't work on some boards, probably a HW BUG */
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if (rate) {
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clk_reg_disable(clk); /*enable bit is inverted */
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if (!clk_wait_for_pll_lock(clk)) {
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clk->rate = CLK_RATE_13MHZ;
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} else {
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clk_reg_enable(clk);
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clk->rate = 0;
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}
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} else {
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clk_reg_enable(clk);
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clk->rate = 0;
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}
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#endif
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return 0;
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}
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/* Clock sources */
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static struct clk osc_13MHz = {
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.name = "osc_13MHz",
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.flags = FIXED_RATE,
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.rate = CLK_RATE_13MHZ,
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};
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static struct clk ck_13MHz = {
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.name = "ck_13MHz",
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.parent = &osc_13MHz,
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.flags = NEEDS_INITIALIZATION,
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.round_rate = &ck_13MHz_round_rate,
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.set_rate = &ck_13MHz_set_rate,
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.enable_reg = OSC13CTRL_REG,
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.enable_shift = 0,
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.rate = CLK_RATE_13MHZ,
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};
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static struct clk osc_32KHz = {
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.name = "osc_32KHz",
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.flags = FIXED_RATE,
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.rate = CLK_RATE_32KHZ,
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};
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/*attached to PLL5*/
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static struct clk ck_1MHz = {
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.name = "ck_1MHz",
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.flags = FIXED_RATE | PARENT_SET_RATE,
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.parent = &ck_13MHz,
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};
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/* PLL1 (397) - provides 13' MHz clock */
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static struct clk ck_pll1 = {
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.name = "ck_pll1",
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.parent = &osc_32KHz,
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.flags = NEEDS_INITIALIZATION,
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.round_rate = &ck_13MHz_round_rate,
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.set_rate = &pll1_set_rate,
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.enable_reg = PLLCTRL_REG,
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.enable_shift = 1,
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.scale_reg = PLLCTRL_REG,
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.rate = CLK_RATE_13MHZ,
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};
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/* CPU/Bus PLL */
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static struct clk ck_pll4 = {
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.name = "ck_pll4",
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.parent = &ck_pll1,
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.flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
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.propagate_next = &per_ck,
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.round_rate = &pll4_round_rate,
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.set_rate = &pll160_set_rate,
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.rate = CLK_RATE_208MHZ,
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.scale_reg = HCLKPLLCTRL_REG,
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.enable_reg = PWRCTRL_REG,
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.enable_shift = 2,
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.parent_switch_reg = SYSCLKCTRL_REG,
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.set_parent = &set_13MHz_parent,
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};
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/* USB PLL */
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static struct clk ck_pll5 = {
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.name = "ck_pll5",
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.parent = &ck_1MHz,
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.flags = NEEDS_INITIALIZATION,
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.round_rate = &pll5_round_rate,
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.set_rate = &pll160_set_rate,
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.scale_reg = USBCTRL_REG,
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.enable_reg = USBCTRL_REG,
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.enable_shift = 18,
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.enable_reg1 = USBCTRL_REG,
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.enable_shift1 = 17,
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};
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/* XPERTTeak DSP PLL */
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static struct clk ck_pll3 = {
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.name = "ck_pll3",
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.parent = &ck_pll1,
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.flags = NEEDS_INITIALIZATION,
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.round_rate = &pll3_round_rate,
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.set_rate = &pll160_set_rate,
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.scale_reg = DSPPLLCTRL_REG,
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.enable_reg = DSPCLKCTRL_REG,
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.enable_shift = 3,
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.enable_reg1 = DSPCLKCTRL_REG,
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.enable_shift1 = 2,
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.parent_switch_reg = DSPCLKCTRL_REG,
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.set_parent = &set_13MHz_parent,
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};
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static struct clk hclk_ck = {
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.name = "hclk_ck",
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.parent = &ck_pll4,
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.flags = PARENT_SET_RATE,
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.set_rate = &hclk_set_rate,
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.round_rate = &hclk_round_rate,
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.scale_reg = HCLKDIVCTRL_REG,
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.rate = 2,
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.user_rate = 2,
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};
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static struct clk per_ck = {
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.name = "per_ck",
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.parent = &ck_pll4,
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.flags = FIXED_RATE,
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.propagate_next = &hclk_ck,
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.set_rate = &per_clk_set_rate,
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.round_rate = &per_clk_round_rate,
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.scale_reg = HCLKDIVCTRL_REG,
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|
.rate = CLK_RATE_13MHZ,
|
|
.user_rate = CLK_RATE_13MHZ,
|
|
};
|
|
|
|
static struct clk m2hclk_ck = {
|
|
.name = "m2hclk_ck",
|
|
.parent = &hclk_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_inv_set_rate,
|
|
.rate = 1,
|
|
.enable_shift = 6,
|
|
.enable_reg = PWRCTRL_REG,
|
|
};
|
|
|
|
static struct clk vfp9_ck = {
|
|
.name = "vfp9_ck",
|
|
.parent = &ck_pll4,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.rate = 1,
|
|
.enable_shift = 4,
|
|
.enable_reg = VFP9CLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk keyscan_ck = {
|
|
.name = "keyscan_ck",
|
|
.parent = &osc_32KHz,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 0,
|
|
.enable_reg = KEYCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk touch_ck = {
|
|
.name = "touch_ck",
|
|
.parent = &osc_32KHz,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 0,
|
|
.enable_reg = TSCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk pwm1_ck = {
|
|
.name = "pwm1_ck",
|
|
.parent = &osc_32KHz,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 0,
|
|
.enable_reg = PWMCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk pwm2_ck = {
|
|
.name = "pwm2_ck",
|
|
.parent = &osc_32KHz,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 2,
|
|
.enable_reg = PWMCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk jpeg_ck = {
|
|
.name = "jpeg_ck",
|
|
.parent = &hclk_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 0,
|
|
.enable_reg = JPEGCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk ms_ck = {
|
|
.name = "ms_ck",
|
|
.parent = &ck_pll4,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 5,
|
|
.enable_reg = MSCTRL_REG,
|
|
};
|
|
|
|
static struct clk dum_ck = {
|
|
.name = "dum_ck",
|
|
.parent = &hclk_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 0,
|
|
.enable_reg = DUMCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk flash_ck = {
|
|
.name = "flash_ck",
|
|
.parent = &hclk_ck,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 1, /* Only MLC clock supported */
|
|
.enable_reg = FLASHCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk i2c0_ck = {
|
|
.name = "i2c0_ck",
|
|
.parent = &per_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 0,
|
|
.enable_reg = I2CCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk i2c1_ck = {
|
|
.name = "i2c1_ck",
|
|
.parent = &per_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 1,
|
|
.enable_reg = I2CCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk i2c2_ck = {
|
|
.name = "i2c2_ck",
|
|
.parent = &per_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 2,
|
|
.enable_reg = USB_OTG_CLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk spi0_ck = {
|
|
.name = "spi0_ck",
|
|
.parent = &hclk_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 0,
|
|
.enable_reg = SPICTRL_REG,
|
|
};
|
|
|
|
static struct clk spi1_ck = {
|
|
.name = "spi1_ck",
|
|
.parent = &hclk_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 4,
|
|
.enable_reg = SPICTRL_REG,
|
|
};
|
|
|
|
static struct clk dma_ck = {
|
|
.name = "dma_ck",
|
|
.parent = &hclk_ck,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 0,
|
|
.enable_reg = DMACLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk uart3_ck = {
|
|
.name = "uart3_ck",
|
|
.parent = &per_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.rate = 1,
|
|
.enable_shift = 0,
|
|
.enable_reg = UARTCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk uart4_ck = {
|
|
.name = "uart4_ck",
|
|
.parent = &per_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 1,
|
|
.enable_reg = UARTCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk uart5_ck = {
|
|
.name = "uart5_ck",
|
|
.parent = &per_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.rate = 1,
|
|
.enable_shift = 2,
|
|
.enable_reg = UARTCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk uart6_ck = {
|
|
.name = "uart6_ck",
|
|
.parent = &per_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 3,
|
|
.enable_reg = UARTCLKCTRL_REG,
|
|
};
|
|
|
|
static struct clk wdt_ck = {
|
|
.name = "wdt_ck",
|
|
.parent = &per_ck,
|
|
.flags = NEEDS_INITIALIZATION,
|
|
.round_rate = &on_off_round_rate,
|
|
.set_rate = &on_off_set_rate,
|
|
.enable_shift = 0,
|
|
.enable_reg = TIMCLKCTRL_REG,
|
|
};
|
|
|
|
/* These clocks are visible outside this module
|
|
* and can be initialized
|
|
*/
|
|
static struct clk *onchip_clks[] = {
|
|
&ck_13MHz,
|
|
&ck_pll1,
|
|
&ck_pll4,
|
|
&ck_pll5,
|
|
&ck_pll3,
|
|
&vfp9_ck,
|
|
&m2hclk_ck,
|
|
&hclk_ck,
|
|
&dma_ck,
|
|
&flash_ck,
|
|
&dum_ck,
|
|
&keyscan_ck,
|
|
&pwm1_ck,
|
|
&pwm2_ck,
|
|
&jpeg_ck,
|
|
&ms_ck,
|
|
&touch_ck,
|
|
&i2c0_ck,
|
|
&i2c1_ck,
|
|
&i2c2_ck,
|
|
&spi0_ck,
|
|
&spi1_ck,
|
|
&uart3_ck,
|
|
&uart4_ck,
|
|
&uart5_ck,
|
|
&uart6_ck,
|
|
&wdt_ck,
|
|
};
|
|
|
|
static int local_clk_enable(struct clk *clk)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
|
|
&& clk->user_rate)
|
|
ret = clk->set_rate(clk, clk->user_rate);
|
|
return ret;
|
|
}
|
|
|
|
static void local_clk_disable(struct clk *clk)
|
|
{
|
|
if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
|
|
clk->set_rate(clk, 0);
|
|
}
|
|
|
|
static void local_clk_unuse(struct clk *clk)
|
|
{
|
|
if (clk->usecount > 0 && !(--clk->usecount)) {
|
|
local_clk_disable(clk);
|
|
if (clk->parent)
|
|
local_clk_unuse(clk->parent);
|
|
}
|
|
}
|
|
|
|
static int local_clk_use(struct clk *clk)
|
|
{
|
|
int ret = 0;
|
|
if (clk->usecount++ == 0) {
|
|
if (clk->parent)
|
|
ret = local_clk_use(clk->parent);
|
|
|
|
if (ret != 0) {
|
|
clk->usecount--;
|
|
goto out;
|
|
}
|
|
|
|
ret = local_clk_enable(clk);
|
|
|
|
if (ret != 0 && clk->parent) {
|
|
local_clk_unuse(clk->parent);
|
|
clk->usecount--;
|
|
}
|
|
}
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int local_set_rate(struct clk *clk, u32 rate)
|
|
{
|
|
int ret = -EINVAL;
|
|
if (clk->set_rate) {
|
|
|
|
if (clk->user_rate == clk->rate && clk->parent->rate) {
|
|
/* if clock enabled or rate not set */
|
|
clk->user_rate = clk->round_rate(clk, rate);
|
|
ret = clk->set_rate(clk, clk->user_rate);
|
|
} else
|
|
clk->user_rate = clk->round_rate(clk, rate);
|
|
ret = 0;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
int clk_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = -EINVAL;
|
|
|
|
if (clk->flags & FIXED_RATE)
|
|
goto out;
|
|
|
|
clock_lock();
|
|
if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
|
|
|
|
clk->user_rate = clk->round_rate(clk, rate);
|
|
/* parent clock needs to be refreshed
|
|
for the setting to take effect */
|
|
} else {
|
|
ret = local_set_rate(clk, rate);
|
|
}
|
|
ret = 0;
|
|
clock_unlock();
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
EXPORT_SYMBOL(clk_set_rate);
|
|
|
|
struct clk *clk_get(struct device *dev, const char *id)
|
|
{
|
|
struct clk *clk = ERR_PTR(-ENOENT);
|
|
struct clk **clkp;
|
|
|
|
clock_lock();
|
|
for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
|
|
clkp++) {
|
|
if (strcmp(id, (*clkp)->name) == 0
|
|
&& try_module_get((*clkp)->owner)) {
|
|
clk = (*clkp);
|
|
break;
|
|
}
|
|
}
|
|
clock_unlock();
|
|
|
|
return clk;
|
|
}
|
|
EXPORT_SYMBOL(clk_get);
|
|
|
|
void clk_put(struct clk *clk)
|
|
{
|
|
clock_lock();
|
|
if (clk && !IS_ERR(clk))
|
|
module_put(clk->owner);
|
|
clock_unlock();
|
|
}
|
|
EXPORT_SYMBOL(clk_put);
|
|
|
|
unsigned long clk_get_rate(struct clk *clk)
|
|
{
|
|
unsigned long ret;
|
|
clock_lock();
|
|
ret = clk->rate;
|
|
clock_unlock();
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(clk_get_rate);
|
|
|
|
int clk_enable(struct clk *clk)
|
|
{
|
|
int ret = 0;
|
|
|
|
clock_lock();
|
|
ret = local_clk_use(clk);
|
|
clock_unlock();
|
|
return ret;
|
|
}
|
|
|
|
EXPORT_SYMBOL(clk_enable);
|
|
|
|
void clk_disable(struct clk *clk)
|
|
{
|
|
clock_lock();
|
|
local_clk_unuse(clk);
|
|
clock_unlock();
|
|
}
|
|
|
|
EXPORT_SYMBOL(clk_disable);
|
|
|
|
long clk_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
long ret;
|
|
clock_lock();
|
|
if (clk->round_rate)
|
|
ret = clk->round_rate(clk, rate);
|
|
else
|
|
ret = clk->rate;
|
|
clock_unlock();
|
|
return ret;
|
|
}
|
|
|
|
EXPORT_SYMBOL(clk_round_rate);
|
|
|
|
int clk_set_parent(struct clk *clk, struct clk *parent)
|
|
{
|
|
int ret = -ENODEV;
|
|
if (!clk->set_parent)
|
|
goto out;
|
|
|
|
clock_lock();
|
|
ret = clk->set_parent(clk, parent);
|
|
if (!ret)
|
|
clk->parent = parent;
|
|
clock_unlock();
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
EXPORT_SYMBOL(clk_set_parent);
|
|
|
|
static int __init clk_init(void)
|
|
{
|
|
struct clk **clkp;
|
|
|
|
/* Disable autoclocking, as it doesn't seem to work */
|
|
__raw_writel(0xff, AUTOCLK_CTRL);
|
|
|
|
for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
|
|
clkp++) {
|
|
if (((*clkp)->flags & NEEDS_INITIALIZATION)
|
|
&& ((*clkp)->set_rate)) {
|
|
(*clkp)->user_rate = (*clkp)->rate;
|
|
local_set_rate((*clkp), (*clkp)->user_rate);
|
|
if ((*clkp)->set_parent)
|
|
(*clkp)->set_parent((*clkp), (*clkp)->parent);
|
|
}
|
|
pr_debug("%s: clock %s, rate %ld\n",
|
|
__func__, (*clkp)->name, (*clkp)->rate);
|
|
}
|
|
|
|
local_clk_use(&ck_pll4);
|
|
|
|
/* if ck_13MHz is not used, disable it. */
|
|
if (ck_13MHz.usecount == 0)
|
|
local_clk_disable(&ck_13MHz);
|
|
|
|
/* Disable autoclocking */
|
|
__raw_writeb(0xff, AUTOCLK_CTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(clk_init);
|